Incremental adaptive match line charging with calibration
AssigneeNetLogic Microsystems, Inc.
InventorsSandeep Khanna, Bindiganavale S. Nataraj, Varadarajan Srinivasan
Life of this patent
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Abstract
A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and an incremental match line charge circuit. The detector circuit generates a feedback signal based on a detected match line voltage. The charge circuit partially pre-charges the match line to an intermediate voltage during a pre-charge phase of a compare operation, and then selectively charges the match line higher towards a supply voltage in response to the feedback signal.
Claims30
A content addressable memory (CAM) device including an array having a plurality of rows, wherein a respective row from among the plurality of rows comprises:
- a plurality of CAM cells coupled to a match line;
- a match detector circuit, coupled to the match line, configured to generate a feedback signal indicative of a match line voltage;
- and
- an incremental charge circuit configured to charge the match line from a first voltage towards a second voltage that is greater than the first voltage during an evaluation phase of a compare operation when the feedback signal indicates a match condition between a search key and data stored in the respective row.
A content addressable memory (CAM) device including a plurality of rows, wherein a respective row from among the plurality of rows comprises:
- a plurality of CAM cells coupled to a match line;
- a match detector circuit, coupled to the match line, configured to generate a feedback signal indicative of a match line voltage;
- and
- a charge circuit configured to partially pre-charge the match line to an intermediate voltage and to selectively charge the match line higher toward a supply voltage that is greater than the intermediate voltage when the feedback signal indicates a match condition between a search key and data stored in the respective row, the charge circuit comprising:
- a first pull-up transistor coupled between the match line and the supply voltage and having a gate responsive to a first pre-charge signal;
- and
- a second pull-up transistor coupled between the match line and the supply voltage and having a gate responsive to a logical combination of the feedback signal and a second pre-charge signal.
A content addressable memory (CAM) device including an array having a plurality of rows, wherein a respective row from among the plurality of rows comprises:
- a plurality of CAM cells coupled to a match line;
- a match detector circuit, coupled to the match line, configured to generate a feedback signal indicative of a match line voltage;
- and
- an incremental charge circuit configured to charge the match line from a first voltage to a second voltage that is greater than the first voltage only during an evaluation phase of a compare operation when the feedback signal indicates a match condition between a search key and data stored in the respective row.
Dependencies are inferred from the claim text.