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AssigneeMicron Technology, Inc.
InventorMichael M. Abraham
Estimating the term…
A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function.
A method of operating a multi-level memory cell, the method comprising:
A controller operable to run programming code stored on a non-transitory computer-readable medium, the programming code comprising:
A memory device comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
Programming or data input circuits: programming voltage switching circuits
Term ended 22 Aug 2026 (estimated)
The invention is directed to the management of pages and blocks of memory within a memory device.
Flash memory devices are routinely used by computer users to store and retrieve programs, files, and/or other electronic data in nonvolatile memory. One type of flash memory device is a NAND Flash device. A NAND flash device typically utilizes a NAND Flash controller to write data to and read data from the NAND Flash device. The NAND Flash controller writes data to and reads data from the NAND Flash device page by page. Pages are typically grouped into blocks, where a block is the smallest erasable unit. For example, and without limitation, a typical memory device contains 2,112 bytes of memory per page and 64 pages of memory are contained in a block. The smallest entity that can be addressed within a page is a byte. A byte consists of eight bits, where a bit is the smallest allocable unit, logically representing a “1” or a “0.”
A typical 2 gigabit (Gb) NAND device is organized as 2,048 blocks. Each block contains 64 pages. Each page has 2,112 bytes total, comprised of a 2,048-byte data area and a 64-byte spare area. The spare area is typically used for Error Correction Code (ECC), wear-leveling information, and other software overhead functions. Typically, there is no limitation as to how the data area and the spare area are partitioned on the page. The NAND Flash control determines the data and spare area partition boundaries.
The foregoing and other advantages and features of the invention will become apparent from the detailed description of exemplary embodiments provided below with reference to the accompanying drawings in which:
FIG. 1 depicts the initial, or erased, state of a multi-level cell NAND Flash memory cell.
FIG. 2 depicts the possible states of the multi-level cell NAND Flash memory cell of FIG. 1 after the lower page has been programmed.
In the following detailed description, reference is made to the accompanying drawings, which are part of the specification, and in which is shown by way of illustration various embodiments whereby the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments may be utilized, and that structural, logical, and electrical changes, as well as changes in the materials used, may be made without departing from the spirit and scope of the present invention. As described in detail below, a desired embodiment of the invention reduces the time required to mark a block for erasure, or other block management functions, by allowing one or more bits in an upper page to be reprogrammed in certain instances.
FIG. 1 illustrates the initial, or erased, state 100 of a Multi-Level Cell NAND Flash memory cell. FIG. 1 shows the value of the bit in the upper page 105 and the value of the bit in the lower page 110 in State 1. As illustrated, both bits have been initialized to “1.” Initializing the value of both bits to “1” is necessary to allow programming of the bits at a later time. In accordance with the rules outlined above, the first bit to be programmed is the bit in the lower page.
FIG. 2 illustrates the two possible states 200, State 1 and State 2a, after the bit in the lower page has been programmed. If the bit in the lower page was programmed to store a “1,” the MLC NAND flash memory cell remains in State 1 indicating that a “1” is stored in the bit in the lower page (which has been programmed) 110 and a “1” is stored in the bit in the upper page (which has not yet been programmed) 105. In this case, since both the initial state and the final state of the MLC NAND flash memory cell are State 1, the voltage level associated with the state remains constant. As shown by FIG. 2, the voltage level of the memory cell increases as the state moves from the left of the figure to the right. If, however, the bit in the lower page was programmed to store a “0,” the MLC NAND flash memory cell moves to State 2a indicating that a “1” is stored in the bit in the upper page (which has not yet been programmed) 205 and a “0” is stored in the bit in the lower page (which has been programmed) 210. In this case the voltage associated with the state increases as depicted in FIG. 2.