Multilayer wiring board

#This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2012-250514 filed Nov. 14, 2012, and Japanese Patent Application No. 2012-256796 filed Nov. 22, 2012.

#The present invention relates to a multilayer wiring board.

#According to an aspect of the invention, there is provided a multilayer wiring board including a signal electrode, a first power supply electrode, and a ground electrode that are provided on a mounting surface and connected to a first element that outputs a signal; an electrode that is provided on the mounting surface and connected to a second element that receives the signal output from the first element through the signal electrode; a ground layer that is provided for both the first and second elements and serves as a return path for a return current of the signal received by the second element; a first power supply layer that is disposed adjacent to the ground layer with a dielectric layer interposed therebetween and supplies electric power to the first element through the first power supply electrode; and a second power supply layer that is provided independently of the first power supply layer and supplies electric power to the second element. The first power supply layer causes the return current that flows through the ground layer to return to the first element through the first power supply electrode as a displacement current between the ground layer and the first power supply layer.

#Exemplary embodiments of the present invention will be described in detail based on the following figures, wherein:

#FIG. 1 is a sectional view of an example of a semiconductor device according to a first exemplary embodiment of the present invention;

#FIG. 2A is a plan view of an example of a fifth layer of a multilayer wiring board according to the first exemplary embodiment;

#Exemplary embodiments of the present invention will be described with reference to the drawings. In the drawings, components having substantially the same functions are denoted by the same reference numerals, and descriptions thereof are omitted to avoid redundancy.

#FIG. 1 is a sectional view illustrating an example the structure of a semiconductor device 1 according to a first exemplary embodiment of the present invention. FIG. 2A is a plan view of a fifth layer of a multilayer wiring board 2 illustrated in FIG. 1. FIG. 2B is a plan view of a sixth layer of the multilayer wiring board 2 illustrated in FIG. 1. FIGS. 2A and 2B illustrate a peripheral region that is not illustrated in FIG. 1.

#The semiconductor device 1 includes a multilayer wiring board 2 having a mounting surface 20a; a mounting board 3 mounted on the mounting surface 20a; a first element 4, such as a processor, that is mounted on the mounting board 3 and outputs a signal through a signal electrode 202; and a second element 5, such as a memory, that is mounted on the multilayer wiring board 2 and receives the signal output from the first element 4.