Decoupling arrangement
AssigneeIntel Corporation
InventorsWilliam L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
Life of this patent
Estimating the term…
Abstract
In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.
Claims26
An apparatus, comprising:
- a decoupling arrangement operative to reduce series inductance between an input port and a decoupling component, the decoupling arrangement comprising:
- an input current path electrically coupling the input port to the decoupling component;
- and
- a return current path electrically coupling the input port to the decoupling component, the input current path and the return current path spaced apart and positioned substantially atop one another.
An apparatus, comprising:
- a decoupling arrangement operative to reduce series inductance between an input port and a decoupling component, the decoupling arrangement comprising:
- a first input current path electrically coupling the input port to the decoupling component, the first input current path in a first plane;
- a second input current path electrically coupling the input port to the decoupling component, the second input current path in a second plane spaced apart from and parallel to the first plane;
- a first return current path electrically coupling the input port to the decoupling component, the first return current path in the first plane;
- a second return current path electrically coupling the input port to the decoupling component, the second return current path in the second plane;
- the first input current path and the second return current path positioned substantially atop one another;
- and
- the second input current path and the first return current path positioned substantially atop one another.
An apparatus, comprising:
- a decoupling arrangement operative to reduce series inductance between an input port and a decoupling component, the decoupling arrangement comprising:
- a matrix of interleaved input current paths and return current paths, each of the interleaved input current paths and return current paths coupling the input port to the decoupling component, the matrix arranged in rows and columns such that:
- each row defines a separate plane wherein adjacent columns within each row alternate between an input current path and a return current path;
- and
- the first column in each row alternates between an input current path and a return current path.
A system, comprising:
- a printed circuit board (PCB);
- a chip component including an input port, the chip component mounted on the PCB;
- a decoupling component mounted on the PCB;
- and
- a decoupling arrangement operative to reduce series inductance between the input port and the decoupling component, the decoupling arrangement comprising:
- an input current path electrically coupling the input port to the decoupling component;
- and
- a return current path electrically coupling the input port to the decoupling component, the input current path and the return current path spaced apart and positioned substantially atop one another.
Dependencies are inferred from the claim text.