Constrained on-the-fly interleaver address generator circuits, systems, and methods

A non-transitory computer-readable storage medium containing software instructions which, when executed b a computer, cause the computer to perform the method comprising:

• interleaving a block of data containing a plurality of subwords, the interleaving including the operations of,
• for each subword having and N columns and M rows defining an array space,
• generating a land address corresponding to one of the N columns;
• providing for each of the N columns a seed value to a linear feedback shift resister of degree 5;
• clocking the linear feedback shift register to generate pseudo random circulant addresses;
• providing a seed value to a linear feedback shift register of degree 6 to generate subcirculant addresses;
• and
• permuting bits of a data block in a first domain to different location in a data block in a second domain using the selected columns, circulant, and sub-circulant addresses.

A method, comprising:

• generating addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis using a plurality of linear feedback shift registers;
• generating lane addresses for each subword;
• and
• generating circulant addresses and sub-circulant addresses to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain using the linear feedback registers.

A method, comprising:

• receiving input message bits and operable to encode these input message bits and store this encoded data on a storage medium;
• generating addresses using a plurality of linear feedback shift registers, the addresses being used to interleave user and parity data in a decoder domain to interleaved codewords in an ISI domain;
• writing the interleaved codewords onto a storage medium;
• reading encoded data stored on the storage medium;
• decoding this encoded data to output the input message bits originally supplied;
• generating addresses using a plurality of linear feedback shift registers, the addresses being used to deinterleave encoded data stored on the storage medium in the ISI domain to deinterleaved codewords in an ISI domain.