Device-like scatterometry overlay targets

A semiconductor target for detecting overlay error between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, the target comprising:

• a plurality of first grating structures having a course pitch that is resolvable by an inspection tool;
• and
• a plurality of second grating structures positioned relative to the first grating structures, wherein the second grating structures have a fine pitch that is smaller than the course pitch, wherein the first and second grating structures are both formed in two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate,
• wherein the first and second grating structures are a plurality of holes formed in two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate and such holes have a plurality of CD values that vary.

A semiconductor target for detecting overlay error between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, the target comprising:

• a plurality of first grating structures having a course pitch that is resolvable by an inspection tool;
• and
• a plurality of second grating structures positioned relative to the first grating structures, wherein the second grating structures have a fine pitch that is smaller than the course pitch, wherein the first and second grating structures are both formed in two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate,
• wherein the course pitch is selected to enhance 1st order diffraction from the first and second grating, while minimizing other diffraction orders,
• wherein the first and second gratings are both formed in a first layer and a second layer, which differs from the first layer, and wherein the first and second set of CD values comprise a subset of CD values that are selected to equalize an amplitude of signals measured from the first and second gratings in both the first and second layers during a scatterometry inspection process.

A method of manufacturing a semiconductor target for detecting overlay error between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, comprising:

• forming a plurality of first grating structures having a course pitch that is resolvable by an inspection tool;
• and
• forming a plurality of second grating structures positioned relative to the first grating structures, wherein the second grating structures have a fine pitch that is smaller than the course pitch, wherein the first and second grating structures are both formed in two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate,
• wherein a duty cycle of the first and second gratings changes with periodicity corresponding to a size of the course pitch.

A method of manufacturing a semiconductor target for detecting overlay error between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, comprising:

• forming a plurality of first grating structures having a course pitch that is resolvable by an inspection tool;
• and
• forming a plurality of second grating structures positioned relative to the first grating structures, wherein the second grating structures have a fine pitch that is smaller than the course pitch, wherein the first and second grating structures are both formed in two or more successive lavers of a substrate or between two or more separately generated patterns on a single layer of a substrate,
• wherein the first and second grating structures are a plurality of holes formed in two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate and such holes have a plurality of CD values that vary.

A method of manufacturing a semiconductor target for detecting overlay error between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, comprising:

• forming a plurality of first grating structures having a course pitch that is resolvable by an inspection tool;
• and
• forming a plurality of second grating structures positioned relative to the first grating structures, wherein the second grating structures have a fine pitch that is smaller than the course pitch, wherein the first and second grating structures are both formed in two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate,
• wherein the first and second gratings are both formed in a first layer and a second layer, which differs from the first layer, and wherein the first and second set of CD values comprise a subset of CD values that are selected to equalize an amplitude of signals measured from the first and second gratings in both the first and second layers during a scatterometry inspection process.