Source driver circuit of liquid crystal display device

A source driver circuit for a liquid crystal display, comprising:

• a power supply voltage input unit in communication with a first power supply voltage and a second power supply voltage, the power supply voltage unit configured to divide the first power supply voltage and the second power supply voltage at a first time when the second power supply voltage is maintained at a middle level into a lower division voltage and an upper division voltage respectively, such that the middle level of the second power supply voltage is lower than a level of the lower division voltage;
• a power supply voltage comparison unit in communication with the power supply voltage unit, the first power supply voltage and the second power supply voltage, the power supply voltage comparison unit configured to receive and to compare the lower division voltage and the upper division voltage and to output an output voltage of a high level in the first time period in which the lower division voltage is higher than the upper division voltage;
• a Schmitt trigger in communication with the power supply voltage comparison unit, the Schmitt trigger configured to receive the output voltage of the high level and to maintain a stable waveform of a reset signal during the first time period without responding to external noise;
• a specific voltage supply unit in communication with the Schmitt trigger and a gate start pulse, the specific voltage supply unit configured to receive the reset signal and to output a voltage of a specific level in a second time period after the first time period and a third time period after the second time period until receiving a first gate start pulse at a fourth time period after the third time period;
• and
• an output buffer unit in communication with the specific voltage supply unit and a valid data source, the output buffer unit configured to receive and to output the voltage of the specific level to a data line of a liquid crystal display panel immediately after power is turned on during the second and third time periods and to output valid data to the data line during the fourth time period.