Gate drive circuit for display device

A gate drive circuit for a display device, comprising:

• at least two clock transmission lines that transmit at least two clock pulses having a phase difference in-between;
• a shift register that outputs scan pulses sequentially based on the clock pulses transmitted from the clock transmission lines;
• and
• a plurality of connecting units that connect the clock transmission lines to the shift register, respectively,
• wherein at least one of the connecting unit includes a zigzagged line that overlaps said corresponding clock transmission line, and
• an overlap preventing hole is provided in a part of the transmission lines overlapped with connecting line of the connecting unit.

A gate drive circuit for a display device, comprising:

• at least two clock transmission lines that transmit at least two clock pulses having a phase difference in-between;
• a shift register that outputs scan pulses sequentially based on the clock pulses transmitted from the clock transmission lines;
• and
• a plurality of connecting units that connect the clock transmission lines to the shift register, respectively,
• wherein at least one of the connecting unit includes a zigzagged line that overlaps said corresponding clock transmission line,
• a first overlap preventing hole is provided in a part of the transmission lines overlapped with connecting line of the connecting unit, and
• a second overlap preventing hole is provided in a corresponding part of the transmission line not overlapped with connecting line of the connecting unit.