Display device

A display device comprising a driving circuit configured to sequentially apply an active potential, which comprises a potential for turning on pixel transistors of the display device, to a plurality of output signal lines extending from an upper output signal line to a lower output signal line, wherein the driving circuit includes

• a main driving circuit configured to output the active potential to one end of one of the output signal lines of the plurality of output signal lines by applying a first clock signal caused by an input of the active potential output from the upper output signal line;
• and
• an auxiliary driving circuit that includes an auxiliary transistor comprising a transistor in which one of a source and a drain is connected to the other end of said one output signal line, and the other of said source and drain is connected to a signal line for said first clock signal,
• wherein the main driving circuit includes a main transistor that is switched so as to apply the clock signal to the output signal line, and
• wherein a gate of the auxiliary transistor is connected to a gate line of the main transistor for the lower output signal line.

A display device comprising:

• a plurality of pixels including pixel transistor;
• a plurality of gate signal lines electrically connected with a gate electrode of the pixel transistor;
• a gate signal line driving circuit for outputting a scanning signal to the plurality of gate signal lines;
• wherein the gate signal line driving circuit includes a main driving circuit and a support circuit,
• the main driving circuit is configured to output a clock signal as the scanning signal to one end of the gate signal line,
• the support circuit electrically connects between the clock signal and the other end of the gate signal line.

A display device comprising a driving circuit configured to sequentially apply an active potential, which comprises a potential for turning on pixel transistors of the display device, to a plurality of output signal lines extending from an upper output signal line to a lower output signal line,

• wherein the driving circuit includes
• a main driving circuit configured to output the active potential to one end of one of the output signal lines of the plurality of output signal lines by applying a first clock signal caused by an input of the active potential output from the upper output signal line;
• an auxiliary driving circuit that includes an auxiliary transistor comprising a transistor in which one of a source and a drain is connected to the other end of said one output signal line, and the other of said source and drain is connected to a signal line for said first clock signal,
• wherein the main driving circuit includes a main transistor that is switched so as to apply the clock signal to the output signal line, and
• wherein a gate of the auxiliary transistor is connected to one of a gate line of the main transistor for the upper output signal line and a gate line of the main transistor for the lower output signal line.