Successive-approximation-register analog-to-digital converter (SAR ADC) and method thereof
AssigneeRealtek Semiconductor Corp.
InventorsJian-Ru Lin, Shih-Hsiun Huang
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Abstract
A SAR ADC and a method thereof are provided. Particularly, in each bit determining duration of last several bit determining durations, a comparer is used to consecutively compare a first potential with a second potential on a sampling and digital-to-analog converting circuit a plurality of times to obtain a plurality of comparison results, and then an SAR control circuit generates a corresponding output bit according to the obtained plurality of comparison results.
Claims19
A successive-approximation-register (SAR) analog-to-digital converting method, comprising:
- generating a first potential by sampling an analog signal;
- generating a plurality of output bits sequentially according to the first potential and a plurality of second potentials occurring consecutively on the digital-to-analog converting circuit by using a comparer, wherein the second potentials correspond to the output bits respectively;
- and
- outputting a digital signal based on the output bits,
- wherein a step of generating a last output bit of the output bits comprises:
- comparing the first potential with a second potential occurring at the last time of the second potentials a plurality of times consecutively by using the comparer, so as to obtain a plurality of first comparison results;
- and
- generating the last output bit according to the first comparison results.
A successive-approximation-register (SAR) analog-to-digital converting method, comprising:
- generating a first potential by sampling an analog signal;
- generating a plurality of output bits sequentially according to the first potential and a plurality of second potentials occurring consecutively on the digital-to-analog converting circuit by using a comparer;
- and
- outputting a digital signal based on the output bits,
- wherein a step of generating last j output bits of the output bits comprises:
- comparing the first potential with a second potential occurring at the last time of the second potentials a plurality of times consecutively by using the comparer, so as to obtain a plurality of first comparison results respectively;
- and
- generating the last j output bits according to the first comparison results of the comparer, wherein j is an integer greater than 1.
A successive-approximation-register (SAR) analog-to-digital converter (ADC), comprising:
- a sampling and digital-to-analog converting circuit, used for generating a first potential by sampling an analog signal;
- a comparer, used for comparing the first potential with a second potential on the sampling and digital-to-analog converting circuit a plurality of times consecutively in a last bit determining duration of a plurality of bit determining durations to obtain a plurality of first comparison results respectively, and comparing the first potential with the second potential once individually in the rest bit determining durations to obtain a corresponding second comparison result;
- and
- an SAR control circuit, comprising:
- a first determining module, used for generating a group of last output bits according to the first comparison results in the last bit determining duration;
- at least one second determining module, wherein each second determining module is corresponding to one of the rest bit determining durations, generates an output bit according to the corresponding second comparison result in the corresponding bit determining duration, and controls the sampling and digital-to-analog converting circuit according to the corresponding second comparison result, so as to adjust the second potential on the sampling and digital-to-analog converting circuit;
- and
- an output logic, used for outputting a digital signal according to the at least one output bit and the group of last output bits.
Dependencies are inferred from the claim text.