Serializer with multiple stages
AssigneeLattice Semiconductor Corporation
InventorsFulong Zhang, Ling Wang, John Schadt
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Abstract
In certain embodiments of the invention, a serializer has a transfer stage that transfers N-bit parallel data from a relatively slow timing domain to a relatively fast timing domain and a serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that buffers the data and can be used to toggle the serializer between an N−1 operating mode and an N+1 operating mode.
Claims20
A serializer adapted to serialize N-bit parallel data, comprising:
- a transfer stage connected to transfer the N-bit parallel data from a relatively slow timing domain to a relatively fast timing domain;
- an update stage connected to receive parallel data from the transfer stage;
- and
- a serializing stage connected to convert parallel data received from the update stage into serial data having N-bit data words,
- wherein the update stage is configurable to cause the serializer to operate in at least an N−1 operating mode or an N+1 operating mode.
A serializer adapted to serialize an N-bit parallel data stream, comprising:
- a stage of transfer registers connected to process parallel data bits from the N-bit parallel data stream based on a first clock signal;
- a stage of update registers connected to process parallel data bits from the stage of transfer registers based on a second clock signal, wherein the second clock signal is faster than the first clock signal;
- and
- a stage of shift registers connected to convert parallel data bits from the stage of update registers into an outgoing serial data stream based on the second clock signal.
A serializer adapted to serialize N-bit parallel data, comprising:
- a first stage connected to receive parallel data;
- and
- a second stage connected to convert parallel data received from the first stage into serial data having N-bit data words,
- wherein an N:1 gearing ratio is achieved by configuring the first stage to cause the serializer to alternately operate in an N−1 operating mode and an N+1 operating mode.
Dependencies are inferred from the claim text.