Mux-based digital delay interpolator

A multi-stage digital delay interpolator comprising:

• an input phase mixing stage comprising
• first and second arrays of multiplexers, each multiplexer configured to
• be input with first and second input voltages, one of the first and second input voltages being a delayed replica of the other input voltage, and
• receive a respective selection signal;
• a plurality of output lines respectively coupled to said first and second arrays of multiplexers,
• first and second output terminals,
• each multiplexer being configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal, and
• a first multiplexer of said first array and a first multiplexer of said second array being configured to output the first input voltage and said second input voltage, respectively,
• corresponding multiplexers of said first array and said second array being configured to be controlled by same selection signals,
• the respective output lines of the multiplexers of said first array configured to be coupled in common to said first output terminal, and the respective output lines of the multiplexers of said second array configured to be coupled in common to said second output terminal;
• and
• an output phase mixing stage coupled in a cascade with said input phase mixing stage and comprising
• a third output terminal,
• an array of multiplexers, and
• a plurality of output lines respectively coupled to said array of multiplexers,
• each multiplexer configured to
• be input with first and second output voltages of a preceding phase mixing stage in the cascade,
• receive a respective selection signal,
• output on the respective output line one of the first and the second output voltages of the preceding phase mixing stage based upon a logic value of the respective selection signal, said plurality of output lines being coupled in common to said third output terminal,
• said third output terminal configured to output a signal delayed by a time delay value based upon a total output capacitance of a number of multiplexers in said array of multiplexers.

A method of making a digital delay interpolator comprising:

• coupling at least one array of multiplexers, each multiplexer to
• be input with first and second input voltages, one of the first and second input voltages being a delayed replica of the other input voltage, and
• receive a respective selection signal;
• coupling a plurality of output lines respectively to the at least one array of multiplexers;
• and
• coupling an output terminal in common to the plurality of output lines, the output terminal to output a signal delayed by a time delay value based upon a total output capacitance of a number of multiplexers in said at least one array of multiplexers;
• each multiplexer of the at least one array thereof to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.