Low power quadrature waveform generator

An apparatus comprising:

• an output circuit comprising:
• a p-channel transistor, wherein a gate of the p-channel transistor is configured to receive a first clock signal;
• and
• a n-channel transistor, wherein the gate of the n-channel transistor is configured to receive a first output signal of a frequency divider, wherein a source of the n-channel transistor is configured to receive a complement of the first clock signal, and wherein the p-channel transistor and the n-channel transistor are connected in series;
• and
• an inverter directly connected to a drain of the n-channel transistor, wherein the inverter is configured to generate a first in-phase reference signal.

A method comprising:

• receiving a first clock signal and a complement of the first clock signal by a frequency divider, a first output circuit and a second output circuit, wherein the frequency divider comprises a first latch and a second latch coupled to the first latch in a toggle-flop configuration, wherein the first latch and the second latch receive the first clock signal and the complement of the first clock signal, wherein the first latch generates a first latch first output, and wherein the second latch generates a second latch first output;
• generating a first in-phase reference signal, by the first output circuit, based on the first clock signal, the complement of the first clock signal, and the first latch first output, wherein the first output circuit comprises:
• a p-channel transistor, wherein a gate of the p-channel transistor receives the first clock signal;
• a n-channel transistor, wherein a drain of the p-channel transistor is directly connected to the drain of the n-channel transistor, wherein the gate of the n-channel transistor receives the first latch first output, and wherein a source of the n-channel transistor receives the complement of the first clock signal;
• and
• a first inverter directly connected to the drain of the n-channel transistor, wherein the first in-phase reference signal is generated at an output of the first inverter;
• and
• generating a first quadrature signal, by the second output circuit, based on the first clock signal, the complement of the first clock signal, and the second latch first output.