Apparatus and method for routing of signals
AssigneeAltera Corporation
InventorsKerry Veenstra, Krishna Rangasayee, Robert Bielby
Life of this patent
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Abstract
A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.
Claims19
A signal routing apparatus comprising:
- a delay locked loop to generate a plurality of phase displaced clock signals;
- and
- a phase controlled write circuit connected to said delay locked loop to store each of a plurality of signals received at the write circuit in response to different phase displaced clock signals received at the write circuit.
A signal routing apparatus comprising:
- a delay locked loop to generate a plurality of phase displaced clock signals;
- a phase controlled read circuit connected to the delay locked loop to sequentially route each of a plurality of signals received at the read circuit in response to different phase displaced clock signals received at the read circuit.
A signaling system comprising:
- a transmitter comprising:
- a first delay locked loop to generate a set of phase displaced clock signals;
- a phase controlled read circuit to sequentially route a set of data signals received at the read circuit in response to said phase displaced clock signals;
- and
- a signaling buffer connected to said phase controlled read circuit to transmit said data signals;
- and
- a receiver comprising:
- a receiver buffer to receive a set of signals and produce a corresponding set of buffered signals;
- a second delay locked loop to generate a set of phase displaced clock signals;
- and
- a phase controlled write circuit connected to said receiver buffer and said delay locked loop to store said set of buffered signals in response to said phase displaced clock signals.
Dependencies are inferred from the claim text.