Method and apparatus for using a synchronous reset pulse to reset circuitry in multiple clock domains

A non-transitory computer-readable medium storing a plurality of instructions which, when executed by a processor, cause the processor to perform operations for using an input synchronous reset pulse, comprising:

• capturing the input synchronous reset pulse for resetting a circuitry comprising a plurality of clock domains, wherein the input synchronous reset pulse is synchronized to a clock of a first clock domain of the plurality of clock domains;
• holding the input synchronous reset pulse that is captured;
• generating a reset pulse for the first clock domain;
• transmitting the reset pulse that is generated to a logic in the first clock domain;
• transmitting the reset pulse that is generated to a delay circuit that holds the reset pulse for a first number of cycles of the clock of the first clock domain;
• monitoring for a rising edge of the reset pulse that has been held for the first number of cycles of the clock of the first domain;
• indicating that the reset for the first clock domain is completed, when the rising edge of the reset pulse is detected;
• transmitting the reset pulse that is generated to a synchronizer of a second clock domain;
• synchronizing the reset pulse that is transmitted from the first clock domain to a clock of the second clock domain;
• transmitting the reset pulse that is synchronized to the clock of the second clock domain to a logic in the second clock domain;
• transmitting the reset pulse that is synchronized to the clock of the second clock domain to a delay circuit that holds the reset pulse for a second number of cycles of the clock of the second clock domain;
• re-synchronizing the reset pulse that is synchronized to the clock of the second clock domain back to the clock of the first clock domain;
• monitoring the reset pulse that is re-synchronized to the clock of the first clock domain for a rising edge;
• indicating that a reset for the second clock domain is completed, when the rising edge is detected for the reset pulse that is re-synchronized to the clock of the first clock domain;
• determining if a resetting of the circuitry is completed for all of the plurality of the clock domains;
• and
• clearing the input synchronous reset pulse that was captured, when the resetting of the circuitry is completed for all of the plurality of the clock domains.

An integrated circuit, comprising:

• a signal capturing module for capturing a synchronous reset pulse for resetting a circuitry comprising a plurality of clock domains, wherein the synchronous reset pulse is synchronized to a clock of a first clock domain of the plurality of clock domains, and for generating a reset pulse for the first clock domain to be transmitted to a logic in the first clock domain and to a delay circuit that holds the reset pulse for a first number of cycles of the clock of the first clock domain;
• a first monitoring module for monitoring a rising edge of the reset pulse that has been held for the first number of cycles of the clock of the first domain, and for indicating that the reset for the first clock domain is completed, when the rising edge of the reset pulse is detected;
• a first synchronizer for synchronizing the reset pulse that is transmitted from the first clock domain to a clock of the second clock domain, wherein the reset pulse that is synchronized to the clock of the second clock domain is transmitted to a logic in the second clock domain and to a delay circuit that holds the reset pulse for a second number of cycles of the clock of the second clock domain;
• a second synchronizer for re-synchronizing the reset pulse that is synchronized to the clock of the second clock domain back to the clock of the first clock domain;
• a second monitoring module for monitoring the reset pulse that is re-synchronized to the clock of the first clock domain for a rising edge, and for indicating that a reset for the second clock domain is completed, when the rising edge is detected for the reset pulse that is re-synchronized to the clock of the first clock domain;
• and
• a logic gate for determining if a resetting of the circuitry is completed for all of the plurality of the clock domains.