Method and apparatus for detecting rising and falling transitions of internal signals of an integrated circuit

An apparatus for detecting a rising transition and a falling transition of an internal signal of an integrated circuit, the apparatus comprising:

• a delay line comprising first to Nth delay elements in series, N being an integer greater than 1, the first delay element receiving the internal signal;
• first latches, inputs of respective ones of the first latches connecting to an input of the first delay element, between two adjacent ones of the delay elements, and an output of the Nth delay elements;
• first to Nth groups of logic gates, each of the first to Nth groups comprising an AND gate and a NOR gate;
• wherein first inputs of the logic gates in the first to Nth groups connect to outputs of the respective ones of the first latches so as to detect signals at inputs of the first to Nth delay elements, respectively;
• wherein second inputs of the logic gates in the first to Nth groups connect to the outputs the respective ones of the first latches so as to detect signals at outputs of the first to Nth delay elements, respectively;
• wherein, in odd numbered groups of the logic gates, the AND gate detects the rising transition, the NOR gate detects the falling transition;
• and
• wherein, in even numbered groups of the logic gates, the AND gate detects the falling transition, the NOR gate detects the rising transition.