Power factor correction circuit having multiple switched-mode converter circuits

A power factor correction circuit comprising:

• a plurality of N switched-mode converter circuits each comprising an nth inductor, where N is at least 2;
• a control circuit coupled to each of the N switched-mode converter circuits,
• wherein the control circuit is configured to allow a current flow through the nth switched-mode converter circuit when the following conditions are fulfilled:
• the current flow through the nth switched-mode converter circuit has decreased to a predefined value;
• and
• a predefined time period has elapsed since the start of a switching pulse for an mth switched-mode converter circuit, where m=n−1 in case n>1 and m=N in case n=1,
• wherein the predefined time period is a predefined fraction of the time period from the start of a previous switching pulse for the nth switched-mode converter circuit to a time when current flow through the nth switched-mode converter circuit has decreased to a predefined value;
• and
• wherein the switching pulse for each of the N switched-mode converter circuits is configured to have a predefined duration.