Electrical connections for chip scale packaging
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Wei Chen, Shih-Wei Liang
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Abstract
Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.
Claims20
A semiconductor device for shielding underlying layers from stresses generated by thermal expansion mismatches between device layers, the device comprising:
- a plurality of device layers including a post-passivation layer, at least two of the device layers having a first direction of coefficient of thermal expansion mismatch;
- and
- a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures, a longest of the plurality of elongated apertures comprising a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.
A semiconductor device comprising:
- a dielectric layer disposed over a substrate, the substrate having a first centermost point from a top down view of the semiconductor device;
- a first opening through the dielectric layer, the first opening comprising a plurality of elongated apertures, the plurality of elongated apertures having a second centermost point from the top down view of the semiconductor device, wherein a longest one of the plurality of elongated apertures, has a length extending substantially perpendicular to a line extending between the first centermost point and the second centermost point, wherein a total width across the plurality of elongated apertures is less than the length;
- and
- an undercontact metallization extending into the plurality of elongated apertures of the first opening.
A method of manufacturing a semiconductor device for shielding underlying layers from stresses generated by thermal expansion mismatches between device layers, the method comprising:
- providing a plurality of device layers including a passivation layer, at least two of the device layers having a first direction of coefficient of thermal expansion mismatch;
- forming a first opening through the passivation layer, the first opening comprising a plurality of elongated apertures, a longest of the plurality of elongated apertures comprising a first dimension, a spacing across the plurality of elongated apertures comprising a second dimension that is less than the first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch;
- and
- forming an undercontact metallization over the first opening.
Dependencies are inferred from the claim text.