Structure and manufacturing method of chip scale package

A chip package comprising:

• a substrate;
• a die having a first side coupled to the substrate, in which an opening through the substrate exposes the first side of the die, and the die comprises a copper layer and a conductive pad at the first side of the die, in the conductive pad is coupled to a first surface of the copper layer, and the conductive pad is exposed by the opening;
• an adhesive material between the substrate and the first side of the die;
• a conductive interconnect coupled to the conductive pad through the opening;
• a dielectric material coupled to a passivation layer on the first side of said die;
• and
• a molding material directly coupled to the die and directly coupled to the substrate.

A chip package comprising:

• a substrate;
• a die having a first side coupled to the substrate, in which an opening through the substrate exposes the first side of the die, and the die comprises a copper layer and a conductive layer at the first side of the die, in which the conductive layer is coupled to a surface of the copper layer, and the conductive layer has a contact point exposed by the opening;
• an adhesive material between the substrate and the first side of the die;
• a conductive interconnect coupled to the contact point of the conductive layer through the opening;
• a dielectric material coupled to a passivation layer on the first side of said die;
• and
• a molding material directly coupled to the die and directly coupled to the substrate.