Wafer-level package and method of manufacturing the same
AssigneeSTS Semiconductor & Telecommunications Co., Ltd.
InventorJung Hwan Chun
Life of this patent
Estimating the term…
Abstract
A wafer-level package and a method of manufacturing the same. The wafer-level package includes a first semiconductor chip on an upper side of which an active surface facing downward is disposed, a redistribution formed on the active surface of the first semiconductor chip, a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique, a copper (Cu) post and a first solder ball sequentially disposed on the redistribution, a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip, and a second solder ball disposed on the first solder ball and electrically connected to an external apparatus.
Claims7
A wafer-level package comprising:
- a first semiconductor chip on an upper side of which an active surface facing downward is disposed;
- a redistribution formed on the active surface of the first semiconductor chip;
- a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique;
- a copper (Cu) post and a first solder ball sequentially disposed on the redistribution;
- a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip;
- and
- a second solder ball disposed on the first solder ball and electrically connected to an external apparatus.
Dependencies are inferred from the claim text.