Integrated circuit package and physical layer interface arrangement
AssigneeVIA Technologies, Inc.
InventorsWei-Chih Lai, Jiang Fan
Life of this patent
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Abstract
An integrated circuit (IC) package includes an IC chip, a package carrier, and a plurality of conductive bumps connecting the IC chip to the package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The active surface has a core area and a signal area surrounding the core area. The IC layered structure includes a first physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The first inner pads are arranged in multiple rows in the signal area.
Claims19
An integrated circuit package comprising:
- an integrated circuit chip;
- a package carrier;
- and
- a plurality of conductive bumps, the integrated circuit chip being connected to the package carrier through the conductive bumps,
- the integrated circuit chip comprising:
- a substrate having an active surface, the active surface having a core area and a signal area surrounding the core area;
- and
- an integrated circuit layered structure configured on the active surface and the integrated circuit layered structure comprising:
- a first physical layer interface comprising:
- a plurality of first bump pads;
- and
- a plurality of first inner pads electrically connected to the first bump pads, respectively, wherein the first inner pads are arranged in multiple rows in the signal area;
- and
- a second physical layer interface comprising:
- a plurality of second bump pads;
- and
- a plurality of second inner pads arranged in multiple rows in the signal area and electrically connected to the second bump pads, respectively,
- wherein the second physical layer interface in the signal area is directly adjacent to the first physical layer interface in the signal area, the core area has four straight sides, the first and second physical layer interfaces are located at only one of the four straight sides of the core area, the second bump pads are minor images of the first bump pads with respect to a first geometric plane perpendicular to the active surface, and the second inner pads are mirror images of the first inner pads with respect to the first geometric plane.
A physical layer interface arrangement suitable for being configured above an active surface of a substrate of an integrated circuit chip, the active surface having a core area and a signal area surrounding the core area, the physical layer interface arrangement comprising:
- a first physical layer interface comprising:
- a plurality of first bump pads;
- and
- a plurality of first inner pads electrically connected to the first bump pads, respectively, wherein the first inner pads are arranged in multiple rows in the signal area;
- and
- a second physical layer interface comprising:
- a plurality of second bump pads;
- and
- a plurality of second inner pads arranged in multiple rows in the signal area and electrically connected to the second bump pads, respectively,
- wherein the second physical layer interface in the signal area is directly adjacent to the first physical layer interface in the signal area, the core area has four straight sides, the first and second physical layer interfaces are located at only one of the four straight sides of the core area, the second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface, and the second inner pads are mirror images of the first inner pads with respect to the first geometric plane.
An integrated circuit package comprising:
- an integrated circuit chip;
- a package carrier;
- and
- a plurality of conductive bumps, the integrated circuit chip being connected to the package carrier through the conductive bumps,
- the integrated circuit chip comprising:
- a substrate having an active surface, the active surface having a core area and a signal area surrounding the core area;
- and
- an integrated circuit layered structure configured on the active surface and the integrated circuit layered structure comprising:
- a first physical layer interface comprising:
- a plurality of first bump pads;
- and
- a plurality of first inner pads electrically connected to the first bump pads, respectively, wherein the first inner pads are arranged in multiple rows in the signal area;
- and
- a second physical layer interface comprising:
- a plurality of second bump pads;
- and
- a plurality of second inner pads arranged in multiple rows in the signal area and electrically connected to the second bump pads, respectively,
- wherein the second physical layer interface in the signal area is directly adjacent to the first physical layer interface in the signal area, the core area has four straight sides, the first and second physical layer interfaces are located at only one of the four straight sides of the core area, the second bump pads are minor images of the first bump pads with respect to a first geometric plane perpendicular to the active surface, and the second inner pads are minor images of the first inner pads with respect to the first geometric plane.
Dependencies are inferred from the claim text.