Semiconductor device for smoothing the voltage of the end face of a drain of a high frequency semiconductor chip
AssigneeKabushiki Kaisha Toshiba
InventorKazutaka Takagi
Life of this patent
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Abstract
According to one embodiment, provided is a semiconductor device includes: a high frequency semiconductor chip; an input matching circuit disposed at the input side of the high frequency semiconductor chip; an output matching circuit disposed at the output side of the high frequency semiconductor chip; a high frequency input terminal connected to the input matching circuit; a high frequency output terminal connected to the output matching circuit, and a smoothing capacitor terminal connected to the high frequency semiconductor chip. The high frequency semiconductor chip, the input matching circuit and the output matching circuit are housed by one package.
Claims9
A semiconductor device comprising:
- a high frequency semiconductor chip;
- an input matching circuit disposed at an input side of the high frequency semiconductor chip;
- an output matching circuit disposed at an output side of the high frequency semiconductor chip;
- a high frequency input terminal connected to the input matching circuit;
- a high frequency output terminal connected to the output matching circuit;
- and
- a smoothing capacitor terminal connected to the high frequency semiconductor chip, wherein
- the high frequency semiconductor chip, the input matching circuit and the output matching circuit are housed by one package, and
- the high frequency semiconductor chip comprises
- a semi-insulating substrate;
- a gate finger electrode, a source finger electrode, and a drain finger electrode configured to be disposed on a first surface of the semi-insulating substrate, and configured to have a plurality of fingers, respectively;
- a plurality of gate terminal electrodes, a plurality of source terminal electrodes, and a drain terminal electrode configured to be disposed on the first surface of the semi-insulating substrate, and configured to tie a plurality of fingers, respectively for each of the gate finger electrode, the source finger electrode, and the drain finger electrode;
- VIA holes, each configured to be disposed at a lower part of each source terminal electrode;
- and
- a ground electrode configured to be disposed on a second surface of the opposite side of the first surface of the semi-insulating substrate, and configured to be connected via the VIA holes to the source terminal electrodes.
Dependencies are inferred from the claim text.