Structure and method for MOSFETS with high-K and metal gate structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJr Jung Lin, Yun-Ju Sun, Shih-Hsun Chang, Chia-Jen Chen, Tomonari Yamamoto, Chih-Wei Kuo, Meng-Yi Sun, Kuo-Chiang Ting
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Abstract
The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure.
Claims16
A semiconductor structure, comprising:
- a semiconductor substrate;
- and
- a gate stack disposed on the semiconductor substrate, wherein the gate stack includes:
- a high k dielectric material layer,
- a capping layer disposed on the high k dielectric material layer, and
- a metal layer disposed on the capping layer, wherein a top surface of the metal layer includes a first width dimension, and wherein an opposing bottom surface of the metal layer includes a second width dimension less than the first width dimension,
- wherein the capping layer and the high k dielectric material layer have a footing structure, wherein the capping layer of the footing structure includes a third width dimension greater than the second width dimension, and wherein the high k dielectric material layer of the footing structure includes a fourth width dimension greater than the third width dimension.
A semiconductor structure, comprising:
- a semiconductor substrate;
- and
- a gate stack disposed on the semiconductor substrate, wherein the gate stack includes:
- a gate dielectric layer including a high k dielectric material layer, wherein a top surface of the gate dielectric layer includes a first width dimension,
- a capping layer disposed on the high k dielectric material layer, wherein a top surface of the capping layer includes a second width dimension less than the first width dimension,
- a metal layer disposed on the capping layer, wherein the metal layer has a reentrant sidewall profile, and wherein a bottom surface of the metal layer includes a third width dimension less than the second width dimension,
- an interfacial layer interposed between the gate dielectric layer and the semiconductor substrate, and
- gate spacers formed on sidewalls of the metal layer and on the top surface of the capping layer and on the top surface of the gate dielectric layer without being formed on a top surface of the interfacial layer.
A semiconductor device comprising:
- a semiconductor substrate;
- a gate dielectric layer disposed on the semiconductor substrate, wherein a top surface of the gate dielectric layer includes a first dimension,
- a capping layer disposed on the gate dielectric layer, wherein a top surface of the capping layer includes a second dimension less than the first dimension, and
- a gate metal layer disposed on the capping layer, wherein a bottom surface of the gate metal layer includes a third dimension less than the second dimension, and wherein a top surface of the gate metal layer includes a fourth dimension greater than the third dimension;
- an interfacial layer interposed between the gate dielectric layer and the semiconductor substrate;
- and
- gate spacers formed on sidewalls of the gate metal layer and on the top surface of the capping layer and on the top surface of the gate dielectric layer without being formed on a top surface of the interfacial layer.
Dependencies are inferred from the claim text.