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US 8,912,589 B2Granted
Methods and apparatuses including strings of memory cells formed along levels of semiconductor material
AssigneeMicron Technology, Inc.
InventorHongmei Wang
Life of this patent
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Abstract
Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed.
Claims24
An apparatus comprising:
- a stack comprising a number of levels of semiconductor material and a number of levels of dielectric material, each of the levels of semiconductor material being doped on at least one respective sidewall of the semiconductor material, a substantial remainder of each of the levels of semiconductor material being doped with a material having a predominant charge carrier that is opposite that of the dopant used on the at least one respective sidewall, each of the levels of semiconductor material being separated from a respective adjacent one of the levels of semiconductor material by at least a respective one of the levels of dielectric material, adjacent ones of the levels of semiconductor material being coupled together by a pillar of semiconductor material, at least one end of the stack being formed into a staircase structure with overlying levels of the stack on the at least one end being stepped back from underlying ones of the number of levels of semiconductor material thereby forming the staircase structure, the at least one respective sidewalls each being coupled to a separate respective sidewall contact line at an appropriate level of the staircase structure, the remainder of each of the levels of semiconductor material being coupled to a separate respective body contact line at an appropriate level of the staircase structure, a respective string of memory cells being formed along each of the levels of semiconductor material.
An apparatus comprising:
- a base substrate having a number of openings formed therein;
- and
- a stack formed between each of the number of openings, each stack having a number of levels of semiconductor material and a number of levels of dielectric material, each level of the number of levels of semiconductor material being separated from an adjacent level of semiconductor material by at least one of the number of levels of dielectric material, at least one end of the stack being formed into a staircase structure with overlying levels of the stack on the at least one end being stepped back from underlying ones of the number of levels of semiconductor material thereby forming the staircase structure, each of the levels of semiconductor material having a first side and an opposing second side;
- and
- at least one string of memory cells being formed along at least one of the first side and the second side of the levels of semiconductor material.
2 more elements
An apparatus comprising:
- a base substrate having a number of openings formed therein;
- and
- a multiple level structure formed between each of the number of openings, each multiple level structure having a number of levels of silicon material and a number of levels of silicon dioxide material, each level of the number of levels of silicon material being separated from an adjacent level of silicon material by at least one of the number of levels of silicon dioxide material, each of the levels of silicon material having a first side and an opposing second side;
- at least one string of memory cells being formed on each of the first side and the second side of the levels of silicon material;
- a number of control gates disposed within the number of openings in the base substrate;
- a charge storage structure disposed between a portion of each of the number of control gates and at least one of the number of levels of silicon material;
- and
- two select gate drain transistors coupled to alternating ones of the number of control gates.
5 more elements
An apparatus comprising:
- a base substrate having a number of openings formed therein;
- and
- a multiple level structure formed between each of the number of openings, each multiple level structure having a number of levels of silicon material and a number of levels of silicon dioxide material, each level of the number of levels of silicon material being separated from an adjacent level of silicon material by at least one of the number of levels of silicon dioxide material, at least one end of the multiple level structure being formed into a staircase structure with overlying levels of the multiple level structure on the at least one end being stepped back from underlying ones of the number of levels of semiconductor material thereby forming the staircase structure, each of the levels of silicon material having a first side and an opposing second side;
- at least one string of memory cells being formed on each of the first side and the second side of the levels of silicon material;
- a number of control gates disposed within the number of openings in the base substrate;
- and
- a charge storage structure disposed between a portion of each of the number of control gates and at least one of the number of levels of silicon material.
4 more elements
An apparatus comprising:
- a stack comprising a number of levels of semiconductor material and a number of levels of dielectric material, each of the levels of semiconductor material being separated from a respective adjacent one of the levels of semiconductor material by at least a respective one of the levels of dielectric material, at least one end of the stack being formed into a staircase structure with overlying levels of the stack on the at least one end being stepped back from underlying ones of the number of levels of semiconductor material thereby forming the staircase structure, a respective string of memory cells being formed along each of the levels of semiconductor material, each of the levels of semiconductor material comprising opposing ones of a first sidewall and a second sidewall, the first sidewall and the second sidewall each having a dopant material of a first type, a substantial remainder of each of the levels of semiconductor material having a dopant material of a second type that has a predominant charge carrier that is opposite that of the dopant material of the first type, a respective one of the strings of memory cells formed along a respective one of the levels of semiconductor material comprises:
- a first string of memory cells formed along the first sidewall of the respective level of semiconductor material;
- and
- a second string of memory cells formed along the second sidewall of the respective level of semiconductor material.
1 more element
Dependencies are inferred from the claim text.