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US 8,912,587 B2Granted
Scalable multi-functional and multi-level nano-crystal non-volatile memory device
AssigneeMicron Technology, Inc.
InventorArup Bhattacharyya
Life of this patent
Estimating the term…
Abstract
A memory cell including a tunnel insulator comprising a plurality of materials, a control gate, a charge blocking material between the tunnel insulator and the control gate, and a discrete trapping material embedded in one of the tunnel insulator or the charge blocking layer.
Claims22
A memory cell comprising:
- a tunnel insulator comprising a plurality of materials wherein a first tunnel insulator material comprises HfO2 and a second tunnel insulator material comprises LaAlO3;
- a control gate;
- a charge blocking material between the tunnel insulator and the control gate;
- and
- a discrete charge trapping material embedded at an interface of the first tunnel insulator material and the second tunnel insulator material, or at an interface of the second tunnel insulator material and the charge blocking material.
2 more elements
A memory cell comprising:
- a tunnel insulator comprising a plurality of materials wherein a first tunnel insulator material comprises HfO2 and a second tunnel insulator material comprises LaAlO3;
- a control gate;
- a charge blocking material between the tunnel insulator and the control gate;
- and
- a discrete charge trapping material embedded in one of the tunnel insulator or the charge blocking material;
- wherein the discrete charge trapping material comprises nano-crystals;
- and
- wherein the nano-crystals have a density in the range of 2×1012/cm2 to 1013/cm2.
5 more elements
A memory cell comprising:
- a tunnel insulator comprising a plurality of materials wherein a first tunnel insulator material comprises HfO2 and a second tunnel insulator material comprises LaAlO3;
- a control gate;
- a charge blocking material between the tunnel insulator and the control gate;
- and
- a discrete charge trapping material embedded in one of the tunnel insulator or the charge blocking material;
- wherein the discrete charge trapping material comprises nano-crystals;
- and
- wherein the nano-crystals have diameters in the range of 3-4 nm.
5 more elements
A memory cell comprising:
- a tunnel insulator comprising a plurality of materials wherein a first tunnel insulator material comprises HfO2 and a second tunnel insulator material comprises LaAlO3;
- a control gate;
- a charge blocking material between the tunnel insulator and the control gate;
- and
- a discrete charge trapping material embedded in one of the tunnel insulator or the charge blocking material;
- wherein the discrete charge trapping material is embedded in the tunnel insulator.
3 more elements
A memory cell comprising:
- a tunnel insulator comprising a plurality of materials wherein a first tunnel insulator material comprises HfO2 and a second tunnel insulator material comprises LaAlO3;
- a control gate;
- a charge blocking material between the tunnel insulator and the control gate;
- and
- a discrete charge trapping material embedded in the charge blocking material at an interface with the tunnel insulator.
2 more elements
A memory cell comprising:
- a first tunnel insulator, the first tunnel insulator comprising first and second materials, wherein the second material of the first tunnel insulator is formed over the first material of the first tunnel insulator;
- a charge blocking material formed over the first tunnel insulator;
- a second tunnel insulator formed over the charge blocking material, the second tunnel insulator comprising the first material and the second material, wherein the first material of the second tunnel insulator is formed over the second material of the second tunnel insulator;
- a control gate formed over the second tunnel insulator;
- and
- a plurality of discrete charge traps embedded in the charge blocking material.
3 more elements
A memory cell comprising:
- a first tunnel insulator, the first tunnel insulator comprising first and second materials;
- a charge blocking material formed over the first tunnel insulator;
- a second tunnel insulator formed over the charge blocking material, the second tunnel insulator comprising first and second materials;
- a control gate formed over the second tunnel insulator;
- and
- a plurality of discrete charge traps embedded in the charge blocking material;
- wherein a first portion of the plurality of discrete charge traps is embedded in a center of the charge blocking material, and wherein a second portion of the plurality of discrete charge traps is embedded at an interface of the charge blocking material and the first tunnel insulator.
4 more elements
A memory cell comprising:
- a first tunnel insulator, the first tunnel insulator comprising first and second materials;
- a charge blocking material formed over the first tunnel insulator;
- a second tunnel insulator formed over the charge blocking material, the second tunnel insulator comprising first and second materials;
- a control gate formed over the second tunnel insulator;
- and
- a plurality of discrete charge traps embedded in the charge blocking material;
- wherein the first portion of the first tunnel insulator and the second portion of the second tunnel insulator comprise HfO2, and wherein the second portion of the first tunnel insulator and the first portion of the second tunnel insulator comprise LaAlO3.
4 more elements
A memory cell comprising:
- a first tunnel insulator, the first tunnel insulator comprising first and second materials;
- a charge blocking material formed over the first tunnel insulator;
- a second tunnel insulator formed over the charge blocking material, the second tunnel insulator comprising first and second materials;
- a control gate formed over the second tunnel insulator;
- and
- a plurality of discrete charge traps embedded in the charge blocking material;
- wherein the charge blocking material comprises HfSiON and the portions of the first and second tunnel insulators that are closest to the HfSiON comprise LaAlO3.
4 more elements
A memory cell comprising:
- a first tunnel insulator, the first tunnel insulator comprising first and second materials;
- a charge blocking material formed over the first tunnel insulator;
- a second tunnel insulator formed over the charge blocking material, the second tunnel insulator comprising first and second materials;
- a control gate formed over the second tunnel insulator;
- and
- a plurality of discrete charge traps embedded in the charge blocking material;
- wherein a first portion of the plurality of discrete charge traps store holes in response to a first gate bias and electrons in response to a second gate bias, and wherein a second portion of the plurality of discrete charge traps store electrons in response to the first gate bias and holes in response to the second gate bias;
- wherein the first gate bias is a positive voltage and the second gate bias is a negative voltage;
- and
- wherein the first portion of the plurality of discrete charge traps is embedded in a center of the charge blocking material, and wherein a second portion of the plurality of discrete charge traps is embedded at an interface of the charge blocking material and the first tunnel insulator.
7 more elements
Dependencies are inferred from the claim text.