PFET polysilicon layer with N-type end cap for electrical shunt

A semiconductor device, comprising:

• a channel region in a semiconductor substrate;
• a gate stack above the channel region and above a part of the semiconductor substrate outside the channel region;
• and
• a doped polysilicon layer above the gate stack, wherein the doped polysilicon layer comprises a first doped portion above the channel region and a second doped portion above the part of the semiconductor substrate outside the channel region, the second doped portion being positioned above a non-active region of the semiconductor device, wherein both the first and second doped portions are in contact with the gate stack, and wherein the first doped portion is doped with a first dopant type and the second doped portion is doped with a second dopant type that is complementary to the first dopant type.

A method for forming a semiconductor device, comprising:

• forming a gate stack in a gate of a field effect transistor, wherein the gate stack is positioned above a channel region of the field effect transistor and above a non-active region of the field effect transistor outside the channel region;
• forming a polysilicon layer on the gate stack in the gate of the field effect transistor;
• providing a first dopant to a first portion of the polysilicon layer above the channel region of the field effect transistor, wherein the first doped portion is in contact with the gate stack;
• and
• providing a second dopant to a second portion of the polysilicon layer above the non-active region of the field effect transistor outside the channel region, wherein the second doped portion is in contact with the gate stack, and wherein the second dopant is complementary to the first dopant.

A method for forming a semiconductor device, comprising:

• forming an amorphous silicon layer on a gate stack, wherein the gate stack has been formed above a channel region in a semiconductor substrate and above a part of the semiconductor substrate outside the channel region;
• providing a first dopant into a first portion of the amorphous silicon layer above the channel region, wherein the first portion is in contact with the gate stack;
• providing a second dopant into a second portion of the amorphous silicon layer above the part of the semiconductor substrate outside the channel region, wherein the second portion is in contact with the gate stack, and wherein the second doped portion is located a selected distance away from the channel region, the selected distance selected such that the second doped portion has little to no affect on the operation of the field effect transistor;
• and
• annealing the semiconductor device.

A system, comprising:

• a semiconductor device comprising a plurality of first field effect transistors and a plurality of second field effect transistors, wherein the first field effect transistors comprise complementary doping to the second field effect transistors, and wherein the first and the second field effect transistors comprise gates with polysilicon layers formed on gate stacks;
• wherein a gate stack in at least one of the first field effect transistors is positioned above a channel region of the first field effect transistor and above a part of the first field effect transistor outside the channel region;
• wherein the polysilicon layer in the gate of the at least one first field effect transistor includes a first doped portion and a second doped portion, wherein the first doped portion is above the channel region of the first field effect transistor and the second doped portion is above the part of the first field effect transistor outside the channel region, wherein both the first and second doped portions are in contact with the gate stack, and wherein the first doped portion is doped with a first dopant type and the second doped portion is doped with a second dopant type that is complementary to the first dopant type;
• and
• wherein the first field effect transistor with the second doped portion comprises a short poly field effect transistor on the semiconductor device in which the field effect transistor comprises a polysilicon layer that is not shared with a neighboring complementary field effect transistor.