Semiconductor device containing HEMT and MISFET and method of forming the same

A method comprising:

• forming a plurality of III-V layers includes on a substrate, the substrate including a metal-insulator-semiconductor field-effect transistor (MISFET) region and a high electron mobility transistor (HEMT) region;
• forming a dielectric cap layer over the plurality of III-V layers;
• patterning the dielectric cap layer to include at least one source opening and at least one drain opening in the MISFET region and to include at least one source opening and at least one drain opening in the HEMT region;
• forming respective source features and drain features in the respective source openings and drain openings in the respective MISFET region and HEMT region;
• forming a protection layer over the dielectric cap layer and the respective source features and drain features;
• patterning the protection layer and the dielectric cap layer to form at least one first gate opening in the MISFET region;
• forming a gate dielectric in the at least one first gate opening;
• patterning the protection layer and the dielectric cap layer to form at least one second gate opening in the HEMT region;
• simultaneously forming a gate electrode layer within the at least one first gate opening and at least one second gate opening.

A method comprising:

• epitaxially growing a first III-V compound layer on a substrate;
• epitaxially growing a second III-V compound layer, different from the first III-V compound layer, on the first III-V compound layer;
• disposing on the second III-V compound layer a GaN layer;
• disposing on the GaN layer a AlGaN layer;
• forming a patterned dielectric cap layer on the AlGaN layer, the patterned dielectric cap layer including openings exposing the AlGaN layer;
• forming source/drain features in the openings;
• forming a protection layer over the source/drain features and over the dielectric cap layer;
• patterning the dielectric cap layer to form second openings exposing the AlGaN layer;
• forming a gate dielectric in selected ones of the second openings, while other ones of the second openings are free of the gate dielectric;
• and
• forming gate conductors extending into respective selected ones of the second openings and respective other ones of the second openings.