Non-volatile semiconductor memory device

A semiconductor memory device comprising a memory cell array, the memory cell array comprising a plurality of first wiring lines, a plurality of second wiring lines, the first and second wiring lines crossing each other, and a plurality of memory cells, the memory cells being disposed in crossing portions of the first and second wiring lines, each memory cell comprising a variable resistance element,

• the memory cell array comprising:
• a plurality of first conductive layers, the first conductive layers extending in a first direction horizontal to a substrate as a longitudinal direction, the first conductive layers being stacked in a direction perpendicular to the substrate, and the first conductive layers functioning as the first wiring lines;
• an interlayer insulating layer provided between the first conductive layers;
• a variable resistance layer formed continuously on side surfaces of the first conductive layers and the interlayer insulating layer, the variable resistance layer functioning as the variable resistance element;
• and
• a columnar conductive layer provided on side surfaces of the first conductive layers and the interlayer insulating layer via the variable resistance layers, the columnar conductive layer extending in a direction perpendicular to a substrate as a longitudinal direction, and the columnar conductive layers functioning as the second wiring lines,
• a second side surface of the interlayer insulating layer being recessed from first side surfaces of the first conductive layers in a direction away from the columnar conductive layers,
• the variable resistance layer being formed continuously on the first and second side surfaces, the variable resistance layer having convex shapes on the first side surfaces.

A method for manufacturing a semiconductor memory device, the semiconductor memory device comprising a memory cell array, the memory cell array comprising a plurality of first wiring lines, a plurality of second wiring lines, the first and second wiring lines crossing each other, and a plurality of memory cells, the memory cells being disposed in crossing portions of the first and second wiring lines, each memory cell comprising a variable resistance element,

• the method comprising:
• alternately depositing first conductive layers for the first wiring lines and an interlayer insulating layer on a substrate,
• forming a trench, the trench having a shape that passes through the first conductive layers and the interlayer insulating layer and extends in a first direction horizontal to the substrate,
• performing wet etching on the first conductive layers and the interlayer insulating layer to recess first side surfaces of the first conductive layers from a second side surface of the interlayer insulating layer or the second side surface from the first side surfaces, and
• forming variable resistance layers for the variable resistance elements on the first side surfaces of the first conductive layers and the second side surface of the interlayer insulating layer and then filling in the trench with a conductive layer.