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US 8,912,517 B2Granted
Resistive switching memory
AssigneeAdesto Technologies Corporation
InventorMichael A. Van Buskirk
Life of this patent
Estimating the term…
Abstract
In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.
Claims27
A memory cell comprising:
- a first resistive switching element comprising a first high resistance state and a first low resistance state and having a first terminal and a second terminal;
- a second resistive switching element comprising a second high resistance state and a second low resistance state and having a first terminal and a second terminal;
- and
- a transistor including a first terminal, a second terminal, and a third terminal, the first terminal of the transistor coupled to the first terminal of the first resistive switching element, the second terminal of the transistor coupled to the first terminal of the second resistive switching element, the third terminal of the transistor coupled to a word line, wherein the first terminals of the first and the second resistive elements are anode or cathode terminals, wherein the second terminals of the first and the second resistive elements are cathode or anode terminals, wherein the first and the second terminals of the transistor are both coupled to anode terminals of the first and the second resistive switching elements or to cathode terminals of the first and the second resistive switching elements.
1 more element
A memory cell comprising:
- a first resistive switching element having a first terminal and a second terminal;
- a second resistive switching element having a first terminal and a second terminal;
- and
- a three terminal transistor having a first terminal, a second terminal, and a third terminal, the first terminal of the three terminal transistor coupled to the first terminal of the first resistive switching element, the second terminal of the three terminal transistor coupled to the first terminal of the second resistive switching element, the third terminal of the three terminal transistor coupled to a word line, wherein the transistor is a PNP transistor, wherein the first terminal of the first resistive switching element is a cathode terminal of the first resistive switching element, and wherein the first terminal of the second resistive switching element is a cathode terminal of the second resistive switching element.
1 more element
A memory cell comprising:
- a first resistive switching element having a cathode terminal and an anode terminal;
- a second resistive switching element having a cathode terminal and an anode terminal;
- and
- a bipolar transistor having a first emitter/collector, a second emitter/collector, and a base, the first emitter/collector coupled to the cathode terminal of the first resistive switching element, the second emitter/collector coupled to the cathode terminal of the second resistive switching element, the base coupled to a word line, the anode terminal of the first resistive switching element coupled to a first bit line of a bit line pair, the anode terminal of the second resistive switching element coupled to a second bit line of the bit line pair, the memory cell configured to store a first or a second memory state.
1 more element
The memory cell of claim1, wherein the transistor comprises a bipolar transistor or a field effect transistor, and wherein both the first and the second terminals of the transistor comprise a source/drain terminal or a emitter/collector terminal.
A method of operating a memory cell, the method comprising:
- providing a memory cell comprising:
- a first resistive switching element comprising a first high resistance state and a first low resistance state and having a first terminal and a second terminal;
- a second resistive switching element comprising a second high resistance state and a second low resistance state and having a first terminal and a second terminal;
- and
- a transistor including a first terminal, a second terminal, and a third terminal, the first terminal of the transistor coupled to the first terminal of the first resistive switching element, the second terminal of the transistor coupled to the first terminal of the second resistive switching element, the third terminal of the transistor coupled to a word line, wherein the first terminals of the first and the second resistive elements are anode or cathode terminals, wherein the second terminals of the first and the second resistive elements are cathode or anode terminals, wherein the first and the second terminals of the transistor are both coupled to anode terminals of the first and the second resistive switching elements or to cathode terminals of the first and the second resistive switching elements, wherein the second terminal of the first resistive switching element is coupled to a first bit line, and wherein the second terminal of the second resistive switching element is coupled to a second bit line;
- applying a positive write voltage at the first bit line and a negative write voltage at the second bit line;
- and
- activating the word line to an intermediate voltage between the positive write voltage and the negative write voltage so as to program the first resistive switching element and erase the second resistive switching element simultaneously.
5 more elements
A memory cell comprising:
- a well region having a first doping type disposed in a semiconductor substrate;
- isolation regions disposed in the semiconductor substrate and dividing the well region into a plurality of word lines;
- a first doped region comprising an opposite second doping type disposed in a word line of the plurality of word lines;
- a second doped region comprising the second doping type disposed in the word line, the second doped region being separated from the first doped region by a portion of the well region, wherein the first doped region, the second doped region, and the portion of the well region form part of a lateral bipolar transistor;
- a first resistive switching element having a first high resistance state and a first low resistance state and comprising a anode/cathode terminal and a corresponding cathode/anode terminal, wherein the anode/cathode terminal of the first resistive switching element is disposed over and coupled to the first doped region;
- and
- a second resistive switching element having a second high resistance state and a second low resistance state and comprising a anode/cathode terminal and a corresponding cathode/anode terminal, wherein the anode/cathode terminal of the second resistive switching element is disposed over and coupled to the second doped region.
4 more elements
Dependencies are inferred from the claim text.