Method for fabricating integrated circuits with patterned thermal adjustment layers for design optimization

A method for fabricating an integrated circuit, said method comprising:

• forming blocks of transistors in a semiconductor substrate;
• strengthening a selected first subset of the blocks of transistors by reducing the channel lengths of the transistors in the first subset of the blocks, wherein reducing the channel lengths of the transistors in the first subset of the blocks comprises:
• forming a patterned layer of material on the semiconductor substrate to cover the selected first subset of the blocks of transistors and leaving a second subset of the blocks of transistors uncovered by the patterned layer of material;
• and
• applying heat to the substrate that heats the selected first subset of the blocks of transistors covered by the patterned layer of material to a different temperature than the second subset of the blocks of transistors that is not covered by the patterned layer of material such that dopant diffuses more in the transistors of the selected first subset of the blocks of transistors than in the transistors of the second subset of the blocks of transistors, the channel lengths of the transistors of the selected first subset of the blocks are reduced by more than the channel lengths of the transistors of the second subset of the blocks of transistors, and the strengths of the transistors of the selected first subset of the blocks are increased;
• and
• removing the patterned layer of material.