Method of fabricating a chip package

A method for manufacturing a chip package, the method comprising:

• forming an electrically insulating material over a chip side;
• selectively removing at least part of the electrically insulating material thereby forming a trench in the electrically insulating material;
• depositing electrically conductive material in the trench wherein the electrically conductive material is electrically connected to at least one contact pad formed over the chip side;
• forming an electrically conductive structure over the electrically insulating material, said conductive structure comprising a first electrically conductive layer and a under bump metallization structure which are homogeneously integrated;
• wherein at least part of the electrically conductive structure is in direct physical and electrical connection with the electrically conductive material;
• and
• depositing a joining structure over the electrically conductive structure.