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US 8,912,085 B1Granted
Method and apparatus for adjusting threshold voltage in a replacement metal gate integration
AssigneeGlobalfoundries Inc.
InventorsBongki Lee, Bharat V. Krishnan, Jinping Liu
Life of this patent
Estimating the term…
Abstract
A methodology for enabling a gate stack integration process that provides additional threshold voltage margin without sacrificing gate reliability and the resulting device are disclosed. Embodiments include conformally forming a margin adjusting layer in a gate trench, forming a metal capping layer on the margin adjusting layer, and forming an n-type work function (nWF) metal layer on the metal capping layer.
Claims17
A method comprising:
- conformally forming a margin adjusting layer in a first gate trench;
- forming a metal capping layer on the margin adjusting layer;
- forming an n-type work function (nWF) metal layer on the metal capping layer;
- conformally forming a high-K (HK) dielectric layer on a bottom surface and sidewalls of the first gate trench and of a second gate trench;
- forming a p-type work function (pWF) metal layer on the HK dielectric layer in the first and second gate trenches;
- removing the pWF metal layer from the first gate trench;
- and
- forming the margin adjusting layer on the HK dielectric layer in the first gate trench.
5 more elements
A device comprising:
- a margin adjusting layer conformally formed in a first gate trench of a replacement metal gate;
- a metal capping layer formed on the margin adjusting layer;
- an n-type work function (nWF) metal layer formed on the metal capping layer;
- a high-K (HK) dielectric layer conformally formed on a bottom surface and sidewalls of the first gate trench and of a second gate trench,
- wherein the margin adjusting layer is formed on the HK dielectric layer of the first gate trench;
- and
- a p-type work function (pWF) metal layer formed on the HK dielectric layer in the second gate trench,
- wherein the margin adjusting layer is formed on the pWF metal layer.
5 more elements
A method comprising:
- forming a high-k (HK) dielectric layer on bottom and side surfaces of N-FET and P-FET gate trenches;
- forming a p-type work function (pWF) metal layer on the HK dielectric layer;
- removing the pWF metal layer from the N-FET gate trench;
- conformally forming a margin adjusting layer in the N-FET and P-FET gate trenches;
- forming a metal capping layer on the margin adjusting layer;
- filling the N-FET and P-FET gate trenches with a silicon (Si) capping layer;
- annealing the Si capping layer;
- subsequently removing the annealed Si capping layer from the N-FET and P-FET gate trenches;
- and
- forming an n-type work function (nWF) metal layer on the metal capping layer.
7 more elements
Dependencies are inferred from the claim text.