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US 8,912,064 B2Granted
Method for forming impurity region of vertical transistor and method for fabricating vertical transistor using the same
AssigneeSK hynix Inc.
InventorsYong Seok Eun, Tae Kyun Kim, Kyong Bong Rouh, Eun Shil Park
Life of this patent
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Abstract
A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
Claims9
A method for forming an impurity region of a vertical transistor, comprising:
- forming a preliminary trench by etching the semiconductor substrate;
- forming an impurity ion junction region in the semiconductor substrate by performing an ion implantation process on the semiconductor substrate exposed by the preliminary trench;
- forming a material layer and filling the material layer in the preliminary trench by using a material which is substantially equal to a material of the semiconductor substrate;
- and
- forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed,
- wherein the etching for forming the trench is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region, and
- wherein the forming of the material layer is performed by an epitaxial growth process.
4 more elements
A method for forming an impurity region of a vertical transistor, comprising:
- preparing a semiconductor substrate having a first region and a second region;
- forming a first mask pattern on the semiconductor substrate, wherein the first mask pattern has an opening exposing a portion of the semiconductor substrate covering the first region and the second region;
- forming a first trench by performing an etching process using the first mask pattern as an etching mask;
- forming an impurity ion junction region in the semiconductor substrate under the bottom of the first trench by performing an ion implantation process using the first mask pattern as a mask for an ion implantation;
- filling the first trench with a material layer formed of a material which is substantially equal to a material of the semiconductor substrate;
- removing the first mask pattern;
- forming a second mask pattern having an opening exposing a portion of the semiconductor substrate covering the second region;
- and
- forming a second trench exposing a side of the first region by etching the portion of the semiconductor substrate covering the second region and the second region using the second mask pattern as an etching mask to form an active region which protrudes upwards and in which a buried bit line junction region is formed at a lower portion of the active region,
- wherein the etching process is performed to remove the impurity ion junction region of the second region, so that the impurity ion junction region remaining in the first region serves as a buried bit line junction region exposed within the second trench, and
- wherein the filling of the first trench is performed by an epitaxial growth process.
8 more elements
A method for fabricating a vertical transistor, comprising:
- forming an impurity ion junction region at a lower portion of the semiconductor substrate by performing an ion implantation process on the semiconductor substrate;
- forming a trench by etching the semiconductor substrate,
- wherein the etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed at a lower portion of the trench and serves as a buried bit line junction region;
- and
- forming a buried bit line by forming an insulation layer at a lower portion of the trench so that the buried bit line is in contact with the buried bit line junction region,
- wherein the forming of the impurity ion junction region comprises:
- preparing a semiconductor substrate having a first region and a second region;
- forming a first mask pattern on the semiconductor substrate, wherein the first mask pattern has an opening exposing a portion of the semiconductor substrate covering the first region and the second region;
- forming a first trench by performing an etching process using the first mask pattern as an etching mask;
- forming an impurity ion junction region in the semiconductor substrate under the bottom of the first trench by performing an ion implantation process using the first mask pattern as a mask for an ion implantation;
- filling the first trench with a material layer formed of a material which is substantially equal to a material of the semiconductor substrate;
- and
- removing the first mask pattern,
- wherein the filling of the first trench is performed by an epitaxial growth process.
11 more elements
Dependencies are inferred from the claim text.