Method for forming recess-free interconnect structure

A method, comprising:

• forming a dielectric material layer on a semiconductor substrate;
• forming an oxygen-rich layer over the dielectric material layer;
• patterning the dielectric material layer and the oxygen-rich layer to form a via in the semiconductor substrate;
• forming a barrier layer in the via and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed;
• forming a metal layer on the barrier layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the via;
• and
• annealing the semiconductor substrate at a predetermined temperature range and at a predetermined pressure to segregate metal oxide to the surface of the metal layer to form a metal-oxide etch stop.

A method comprising:

• forming a plurality of first metal features embedded in a dielectric material layer on a semiconductor substrate;
• forming an oxygen rich layer encircling an upper region of respective ones of the plurality of first metal features;
• annealing the plurality of first metal features and the oxygen rich layer to segregate metal oxide to the surface of the respective ones of the plurality of first metal features to form a respective metal-oxide etch stop around the respective ones of the plurality of first metal features;
• and
• forming a plurality of second metal features embedded in the dielectric material layer, respective ones of the plurality of second metal features being substantially aligned with respective ones of the plurality of first metal.