# US 8,902,954 B2 · Video serializer/deserializer having selectable multi-lane serial interface > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,902,954 B2 - Document ID: US8902954B2 - Status: Granted - Kind: B2 - Application number: 13/664,684 - Filed: 2012-10-31 - Published: 2013-03-07 - Granted: 2014-12-02 - Earliest claimed: 2006-09-01 - Assignees: Semtech Canada Corporation - Applicants: Semtech Canada Corporation - Inventors: John Hudson; Ryan Eckhardt - Web page: https://patentgrep.com/patent/US8902954B2 ## CPC - H04N 21/2381: Adapting the multiplex stream to a specific network, e.g. an Internet Protocol [IP] network {(transmission of MPEG streams over ATM H04L12/5601)} - H04N 21/643: Communication protocols {(network streaming protocols, e.g. real-time transport protocol [RTP] or real-time control protocol [RTCP], H04L65/65)} - G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)} - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A video processing system may include: a video deserializer having (i) an input for receiving a serial data stream containing video data and (ii) a serial to pseudo-parallel converter, coupled to the serial data stream, for generating from the serial data stream a plurality of serial data output streams through a plurality of serial output lanes; a video serializer having (i) a plurality of inputs for receiving serial data streams and (ii) a pseudo-parallel to serial converter, coupled to the plurality of input serial data streams, for generating a single serial data stream from the plurality of input serial data streams; and a programmable video processing device, coupled to the video deserializer and the video serializer, and having a plurality of interface pins for receiving the plurality of serial output lanes from the deserializer and for transmitting the plurality of serial data streams to the serializer. ## Claims ### Claim 1 A video deserializer device comprising: an input for receiving an input serial data stream containing video data; a serial to pseudo-parallel converter configured to deserialize the input serial data stream to generate a plurality of output serial data streams through a plurality of output serial lanes, wherein each output serial lane comprises a differential pair of electrical lines, and each output serial data stream comprises a low voltage differential signal (LVDS) that comprises a pair of complementary signals conducted over the differential pair of electrical lines of a corresponding one of the output serial lanes, and each output serial data streams includes a portion of the input serial data stream; and a lane-select input configured to receive a lane-select signal for setting the number of the output serial data streams to be generated by the serial to pseudo-parallel converter. ### Claim 2 (depends on 1) The video deserializer device of claim 1, further comprising: a clocking circuit for extracting a clock signal from the input serial data stream; and a re-timing circuit, coupled to the input serial data stream and the extracted clock signal, for generating a re-timed serial data stream that is received by the input. ### Claim 3 (depends on 2) The video deserializer device of claim 2, wherein the clocking circuit comprises: a clock extractor for extracting the clock signal from the input serial data stream; and a clock and data recovery circuit coupled to both (i) the extracted clock signal and (ii) an external reference clock for generating a retiming clock that is coupled to the re-timing circuit. ### Claim 4 (depends on 1) The video deserializer device of claim 1, wherein the lane-select input is a three-bit input and enables selection of two output serial data streams, four output serial data streams and five output serial data streams. ### Claim 5 (depends on 4) The video deserializer device of claim 4, further comprising: a manual/automatic select input configured to input a manual/automatic select signal that selects between (1) the input lane-select signal setting the number of output serial data streams to generate and (2) the serial to pseudo-parallel converter automatically determining, based on a format of the input serial data stream, the number of output serial data streams to generate. ### Claim 6 (depends on 1) The video deserializer device of claim 1, further comprising an equalizer that generates the input serial data stream. ### Claim 7 (depends on 1) The video deserializer device of claim 1, further comprising a descrambler that descrambles the input serial data stream. ### Claim 8 (depends on 7) The video deserializer device of claim 7, wherein the descrambler operates in the serial domain. ### Claim 9 (depends on 7) The video deserializer device of claim 7, further comprising a serial to parallel converter that converts the input serial data stream to a parallel output to the descrambler, wherein the descrambler operates in the parallel domain. ### Claim 10 (depends on 9) The video deserializer device of claim 9, wherein the serial to pseudo-parallel converter converts the descrambled parallel output into the plurality of output serial data streams. ### Claim 11 (depends on 9) The video deserializer device of claim 9, further comprising a word aligner that word aligns the parallel output. ### Claim 12 (depends on 1) The video deserializer device of claim 1, wherein the plurality of output serial data streams are configured to be input to a field-programmable gate array FPGA video processor. ### Claim 13 (depends on 1) The video deserializer device of claim 1, wherein the serial to pseudo-parallel converter is configured to automatically determine, based on a format of the serial input data, the number of the output serial data streams to generate. ### Claim 14 A video serializer device comprising: a plurality of differential input serial lanes for receiving a plurality of input serial data streams, wherein each input serial lane comprises a differential pair of electrical lines, and each input serial data stream comprises a low voltage differential signal (LVDS) that comprises a pair of complementary signals conducted over the differential pair of electrical lines of a corresponding one of the input serial lanes; a pseudo-parallel to serial converter configured to serialize the input serial data streams to generate a single output serial data stream that includes data from all of the input serial data streams; and a lane-select input configured to receive a lane-select signal that sets the number of the input serial data streams to be serialized by the pseudo-parallel to serial converter. ### Claim 15 (depends on 14) The video serializer device of claim 14, further comprising: a clocking circuit for receiving a reference clock; and a plurality of re-timing circuits, coupled to the plurality of input serial data streams, for retiming the input serial data streams prior to the input serial data streams being serialized. ### Claim 16 (depends on 14) The video serializer device of claim 14, further comprising a cable driver coupled to the single output serial data stream for generating a differential output serial data stream. ### Claim 17 (depends on 14) The video serializer device of claim 14, wherein the pseudo-parallel to serial converter performs a de-skewing operation on the plurality of input serial data streams. ### Claim 18 (depends on 14) The video serializer device of claim 14, wherein the lane-select input is a three-bit input and enables selection of two input serial data streams, four input serial data streams and five input serial data streams. ### Claim 19 A method performed by a video deserializer device, the method comprising: receiving an input serial data stream containing video data; deserializing the input serial data stream to generate a plurality of output serial data streams through a plurality of differential output serial lanes, wherein each output serial lane comprises a differential pair of electrical lines, and each output serial data stream comprises a low voltage differential signal (LVDS) that comprises a pair of complementary signals conducted over the differential pair of electrical lines of a corresponding one of the output serial lanes, and each output serial data stream includes a portion of the video data contained in the input serial data stream; and receiving a lane-select signal for setting the number of the output serial data streams to be generated. ### Claim 20 (depends on 19) The method of claim 19, wherein the lane-select signal is through a three-bit input that enables selection of two output serial data streams, four output serial data streams and five output serial data streams. ### Claim 21 (depends on 20) The method of claim 20, further comprising: receiving a manual/automatic select signal that selects between (1) the input lane-select signal setting the number of output serial data streams to generate and (2) the video deserializer device automatically determining, based on a format of the input serial data stream, the number of output serial data streams to generate. ### Claim 22 (depends on 19) The method of claim 19, further comprising: automatically determining, based on a format of the input serial data stream, the number of the output serial data streams to generate. ### Claim 23 A method performed by a video serializer device, the method comprising: receiving a plurality of input serial data streams through a plurality of differential input serial lanes, wherein each input serial lane comprises a differential pair of electrical lines, and each input serial data stream comprises a low voltage differential signal (LVDS) that comprises a pair of complementary signals conducted over the differential pair of electrical lines of a corresponding one of the input serial lanes; serializing the input serial data streams to generate a single output serial data stream that includes data from the input serial data streams; and receiving a lane-select signal that sets the number of the input serial data streams to be serialized. ### Claim 24 (depends on 23) The method of claim 23, wherein the received lane-select signal is through a three-bit input that is configured to enable selection of two output serial data streams, four output serial data streams and five output serial data streams. ### Claim 25 (depends on 23) The method of claim 23, further comprising: performing a de-skewing operation on the input serial data streams.