Transistors with high concentration of boron doped germanium

A transistor device, comprising:

• a substrate having a channel region;
• a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode;
• and
• source and drain regions formed in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under the gate dielectric layer and/or a corresponding one of the spacers, wherein the source and drain regions and corresponding tip regions comprise a boron doped germanium layer having a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 1E20 cm−3;
• wherein the boron doped germanium layer has a bilayer construction comprising a boron doped silicon germanium portion and a boron doped germanium cap thereon;
• and
• wherein the boron doped silicon germanium portion has a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 1E20 cm−3.

A transistor device, comprising:

• a substrate having a channel region;
• a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode;
• and
• source and drain regions formed in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under the gate dielectric layer and/or a corresponding one of the spacers, wherein the source and drain regions and corresponding tip regions comprise a boron doped germanium layer having a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 1E20 cm−3;
• wherein the boron doped germanium layer has a bilayer construction comprising a boron doped silicon germanium portion and a boron doped germanium cap thereon;
• and
• wherein the boron doped silicon germanium portion has a fixed germanium concentration, and the device further comprises a buffer between the boron doped silicon germanium portion and the boron doped germanium cap, the buffer having a germanium concentration that is graded from a base level concentration compatible with the boron doped silicon germanium portion to a high concentration in excess of 50 atomic %, and a boron concentration that is graded from a base level concentration compatible with the boron doped silicon germanium portion to a high concentration in excess of 1E20 cm−3.

A transistor device, comprising:

• a substrate having a channel region;
• a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode;
• source and drain regions formed in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under the gate dielectric layer and/or a corresponding one of the spacers, wherein the source and drain regions and corresponding tip regions comprise a boron doped germanium layer having a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 2E20 cm−3;
• metal-germanide source and drain contacts;
• and
• a buffer between the substrate and the boron doped germanium layer, wherein the buffer has a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 95 atomic %, and a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 2E20 cm−3.

A transistor device, comprising:

• a substrate having a channel region;
• a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode;
• source and drain regions formed in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under the gate dielectric layer and/or a corresponding one of the spacers, wherein the source and drain regions and corresponding tip regions comprise a boron doped germanium layer having a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 2E20 cm−3;
• and
• metal-germanide source and drain contacts;
• wherein the boron doped germanium layer has a bilayer construction comprising a boron doped silicon germanium portion and a boron doped germanium cap thereon;
• wherein the boron doped silicon germanium portion has a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 50 atomic %, and the boron doped germanium cap has a germanium concentration in excess of 95 atomic %;
• and
• wherein the boron doped silicon germanium portion has a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 2E20 cm−3.

A transistor device, comprising:

• a substrate having a channel region;
• a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode;
• source and drain regions formed in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under the gate dielectric layer and/or a corresponding one of the spacers, wherein the source and drain regions and corresponding tip regions comprise a boron doped germanium layer having a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 2E20 cm−3;
• and
• metal-germanide source and drain contacts;
• wherein the boron doped germanium layer has a bilayer construction comprising a boron doped silicon germanium portion and a boron doped germanium cap thereon;
• and
• wherein the boron doped silicon germanium portion has a fixed germanium concentration, and the device further comprises a thin buffer between the boron doped silicon germanium portion and the boron doped germanium cap, the buffer having a germanium concentration that is graded from a base level concentration compatible with the boron doped silicon germanium portion to a high concentration in excess of 50 atomic %, and a boron concentration that is graded from a base level concentration compatible with the boron doped silicon germanium portion to a high concentration in excess of 2E20 cm−3, the buffer having a thickness of less than 100 Angstroms.

A method for forming a transistor device, comprising:

• providing a substrate having a channel region;
• providing a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode;
• forming source and drain regions in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under the gate dielectric layer and/or a corresponding one of the spacers, wherein the source and drain regions and corresponding tip regions comprise a boron doped germanium layer having a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 1E20 cm−3;
• and
• providing a buffer between the substrate and the boron doped germanium layer, wherein the buffer has a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 1E20 cm−3.

A method for forming a transistor device, comprising:

• providing a substrate having a channel region;
• providing a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode;
• and
• forming source and drain regions in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under the gate dielectric layer and/or a corresponding one of the spacers, wherein the source and drain regions and corresponding tip regions comprise a boron doped germanium layer having a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 1E20 cm−3;
• wherein the boron doped germanium layer has a bilayer construction comprising a boron doped silicon germanium portion and a boron doped germanium cap thereon;
• and
• wherein the boron doped silicon germanium portion has a fixed germanium concentration, and the method further comprises providing a buffer between the boron doped silicon germanium portion and the boron doped germanium cap, the buffer having a germanium concentration that is graded from a base level concentration compatible with the boron doped silicon germanium portion to a high concentration in excess of 50 atomic %, and a boron concentration that is graded from a base level concentration compatible with the boron doped silicon germanium portion to a high concentration in excess of 1E20 cm−3.