Processor that executes a plurality of threads by promoting efficiency of transfer of data that is shared with the plurality of threads

A control method used in a processor that executes a plurality of threads, the processor including a register, the control method comprising:

• storing, in the register and in association, an instruction address, a data address, and usage information indicating whether or not writing into a memory area has been completed;
• monitoring a fetch address of an instruction fetch in one thread, and when the fetch address matches the instruction address stored in the register, updating the usage information stored in the register with a value indicating that writing into the memory area has been completed;
• monitoring a read address for execution of a read instruction of another thread, and when the read address matches the data address stored in the register, suppressing execution of the read instruction when the usage information stored in the register indicates that writing into the memory area has not been completed;
• and
• converting a virtual address to a physical address, the virtual address being received when the data is read, and determining whether or not a read address check flag of the virtual address is ON, wherein
• monitoring pertaining to the read instruction is performed only when the read address check flag is determined to be ON.

An image processing apparatus that processes an image by using a plurality of threads, the image processing apparatus comprising:

• a register configured to store, in association, an instruction address, a data address, and usage information indicating whether or not writing into a memory area has been completed;
• a setting unit configured to monitor a fetch address of an instruction fetch in one thread, and when the fetch address matches the instruction address stored in the register, update the usage information stored in the register with a value indicating that writing into the memory area has been completed;
• a control unit configured to monitor a read address for execution of a read instruction of another thread, and when the read address matches the data address stored in the register, suppress execution of the read instruction when the usage information stored in the register indicates that writing into the memory area has not been completed;
• and
• an address conversion unit configured to convert a virtual address to a physical address, the virtual address being received when the data is read, wherein
• when converting the virtual address, the address conversion unit determines whether or not a read address check flag of the virtual address is ON, and
• the control unit performs monitoring pertaining to the read instruction only when the address conversion unit has determined that the read address check flag is ON.