US 8,898,652 B2 · Cache metadata for accelerating software transactional memory

Abstract

Various technologies and techniques are disclosed for providing a hardware accelerated software transactional memory application. The software transactional memory application has access to metadata in a cache of a central processing unit that can be used to improve the operation of the STM system. For example, open read barrier filtering is provided that uses an opened-for-read bit that is contained in the metadata to avoid redundant open read processing. Similarly, redundant read log validation can be avoided using the metadata. For example, upon entering commit processing for a particular transaction, a get-evictions instruction in an instruction set architecture of the central processing unit is invoked. A retry operation can be optimized using the metadata. The particular transaction is aborted at a current point and put to sleep. The corresponding cache line metadata in the metadata are marked appropriately to efficiently detect a write by another CPU.

Claims19

Dependent claims

A computer-readable medium storing computer-executable instructions for causing a computer to perform operations comprising:

providing a hardware accelerated software transactional memory application that has access to metadata in a central processing unit (CPU) cache;
determining that a retry operation should be used for a particular transaction of a processor;
aborting the particular transaction at a current point, the aborting comprising rolling back updates in the particular transaction;
putting the particular transaction to sleep in response to aborting the particular transaction by executing a pause instruction to enter a low power state;
after the particular transaction is aborted, marking cache line metadata in the metadata corresponding to watched cache lines in the aborted particular transaction;
waking up the particular transaction in response to another transaction evicting a marked cache line corresponding to the watched cache lines in the aborted transaction;
and
retrying the particular transaction.

5 more elements

A computer system comprising:

a central processing unit (CPU) including a plurality of logical processors;
a CPU cache including:
a plurality of cache lines, and
cache line metadata corresponding to each cache line;
and
a computer-readable medium storing computer-executable instructions for causing the CPU to perform operations comprising:
providing a hardware accelerated software transactional memory application that has access to the cache line metadata;
determining that a retry operation should be used for a particular transaction of the CPU;
aborting the particular transaction at a current point, the aborting comprising rolling back updates in the particular transaction;
putting the particular transaction to sleep in response to aborting the particular transaction by executing a pause instruction to enter a low power state;
after the particular transaction is aborted, marking cache line metadata in the metadata corresponding to watched cache lines in the aborted particular transaction;
waking up the particular transaction in response to another transaction evicting a marked cache line corresponding to the watched cache lines in the aborted transaction;
and
retrying the particular transaction.

11 more elements

Dependencies are inferred from the claim text.

Cache metadata for accelerating software transactional memory

Life of this patent

Cache metadata for accelerating software transactional memory

Life of this patent

Abstract

Claims19