Integrated circuit device with reduced leakage and method therefor
AssigneeFreescale Semiconductor, Inc.
InventorsPuneet Sharma, Magdy S. Abadir, Scott P. Warrick
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Abstract
A method includes preferentially placing fill regions adjacent to transistors of a particular conductivity type, such as p-channel transistors, for a plurality of standard cell instances of a device design. The method also includes evaluating all transistors of the first conductivity type prior to evaluating any transistors of a second conductivity type. The second conductivity type is opposite the first conductivity type. For each transistor being evaluated, it is determined whether a criterion is me. A fill region is placed within a field isolation region adjacent to the transistor if the criterion is met.
Claims18
A method implemented at a computer aided design tool comprising:
- preferentially placing fill regions adjacent to transistors of a first conductivity type for a plurality of standard cell instances of a device design to reduce leakage of the plurality of standard cell instances, wherein preferentially placing fill regions further comprises:
- evaluating, using a computer, all transistors of the first conductivity type for the plurality of standard cell instances prior to evaluating any transistors of a second conductivity type for the plurality of standard cell instances, the second conductivity type opposite the first conductivity type;
- and
- for each transistor being evaluated, determining if a criterion comprising a design rule that governs surface planarity is met, and placing the fill region within a field isolation region and adjacent to the transistor being evaluated in response to the criterion being met.
An integrated circuit data processing device comprising:
- a plurality of standard cell instances, each standard cell instance including a first p-channel transistor and a first n-channel transistor;
- and
- a plurality of fill regions defined within field isolation regions, wherein a majority of the fill regions is in closer physical proximity to p-channel transistors than to n-channel transistors and located at a distance from an active diffusion region of the corresponding p-channel transistor that does not exceed four times the value of a minimum permissible width of a shallow trench isolation feature, and wherein each fill region fills an opening of the field isolation region.
A non-transitory computer readable medium embodying a software program, the software program comprising executable instructions configured to manipulate at least one processor to:
- identify transistors of a first conductivity type at instance of standard cells of a device design, the standard cells including transistors of a first conductivity type and transistors of a second conductivity type that is opposite the first conductivity type;
- and
- place fill regions adjacent to transistors of the first conductivity type preferentially, as opposed to placing fill regions adjacent to transistors of the second conductivity type, at locations that reduce leakage of the transistors of the first conductivity type, wherein preferentially placing fill regions further comprises placing fill regions adjacent to transistors of the second conductivity type only after exhausting opportunities to place fill regions adjacent to transistors of the first conductivity type, and only when additional fill regions are required to be placed based on a criterion comprising a design rule that governs surface planarity.
Dependencies are inferred from the claim text.