Layout pattern correction for integrated circuits
AssigneeGlobalfoundries Inc.
InventorsRani Abou Ghaida, Ahmed Mohyeldin, Piyush Pathak, Swamy Muddu, Vito Dai, Luigi Capodieci
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Abstract
A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.
Claims20
A method comprising:
- determining a portion of a layout of an integrated circuit (IC) design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections;
- determining a plurality of sets of the plurality of design connections based on the plurality of routes;
- and
- determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the plurality of sets.
An apparatus comprising:
- a processor;
- and
- memory including computer program code for a program,
- the memory and the computer program code configured to, with the processor, cause the apparatus to perform at least the following,
- determine a portion of a layout of an integrated circuit (IC) design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections;
- determine a plurality of sets of the plurality of design connections based on the plurality of routes;
- and
- determine a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the plurality of sets.
A method comprising:
- determining a portion of a layout of an integrated circuit (IC) design, the portion comprising a first pattern including a first route connecting a first set of design connections and a second route connecting a second set of design connections;
- associating the first and second sets of design connections with the first and second routes, respectively;
- and
- determining, by a processor, a second pattern for the portion based on the associating, the second pattern including a route connecting design connections of the first set.
Dependencies are inferred from the claim text.