Logic circuit design method, logic circuit design program, and logic circuit design system
AssigneeKabushiki Kaisha Toshiba
InventorsMasahisa Miyake, Kenji Yoshida, Kazumasa Nomura
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Abstract
According to one embodiment, a logic circuit design method of an embodiment includes generating logical data corresponding to register transfer level description, based on design data containing the register transfer level description, and generating constraint conditions designating circuit data which satisfies a predetermined condition among plural gate level circuit data logically equivalent to the logical data, based on the design data, and generating gate level circuit data based on the logical data under the constraint conditions.
Claims15
A computer-implemented method of generating a net list, the method comprising:
- generating logical data for each of portions corresponding to blocks of a register transfer level description relevant to operation of a gate logic circuit, accounting for an order of priority in the register transfer level description, based on a source code comprising the register transfer level description;
- generating one or more constraint conditions designating circuit data which satisfies a condition among a plurality of gate level circuit data logically equivalent to the logical data for each of the portions, based on the source code, the generating the one or more constraint conditions comprising setting a fixing attribute for at least one of the portions describing an AND logic operation on
- an asynchronous signal or a multi-cycle signal, and
- an enable signal or a select signal, the fixing attribute configured to exclude performance of optimization on the at least one of the portions;
- and
- generating the net list based on optimization of the logical data under the one or more constraint conditions including the fixing attribute,
- the method performed programmatically by a design system that comprises one or more computers.
A non-transitory, computer-readable storage medium having stored thereon a net list generating program that, when executed by an electronic computer, causes the computer to execute functions comprising:
- generating logical data for each of portions corresponding to blocks of a register transfer level description relevant to operation of a gate logic circuit, accounting for an order of priority in the register transfer level description, based on source code comprising the register transfer level description;
- generating one or more constraint conditions designating circuit data which satisfies a condition among a plurality of gate level circuit data logically equivalent to the logical data for each of the portions, based on the source code, the generating the one or more constraint conditions comprising setting a fixing attribute for at least one of the portions describing an AND logic operation on
- an asynchronous signal or a multi-cycle signal, and
- an enable signal or a select signal the fixing attribute to configured to exclude performance of optimization on the at least one of the portions;
- and
- generating the net list based on optimization of the logical data under the one or more constraint conditions including the fixing attribute.
A net list design system including one or more computing devices comprising:
- a logical data generator configured to generate logical data for each of portions corresponding to blocks of a register transfer level description relevant to operation of a gate logic circuit, accounting for an order of priority in the register transfer level description, based on source code comprising the register transfer level description;
- a constraint-condition unit configured to generate one or more constraint conditions designating circuit data which satisfies a condition among a plurality of gate level circuit data logically equivalent to the logical data for each of the portions, based on the source code, the one or more constraint conditions comprising a fixing attribute for at least one of the portions describing an AND logic operation on
- an asynchronous signal or a multi-cycle signal, and
- an enable signal or a select signal,
- the fixing attribute configured to inhibit performance of optimization on the at least one of the portions;
- and
- an optimization unit configured to generate the net list based on the logical data under the one or more constraint conditions including the fixing attribute.
Dependencies are inferred from the claim text.