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US 8,898,553 B1Granted
Log-likelihood-ratio (LLR) table calibration
AssigneeMarvell International Ltd.
InventorsNedeljko Varnica, Seo-How Low, Gregory Burd
Life of this patent
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Abstract
Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.
Claims20
A method comprising:
- performing a plurality of read cycles on a plurality of memory cells of a memory;
- based on performing the plurality of read cycles on the plurality of memory cells of the memory, constructing a plurality of bin histograms, wherein each bin histogram of the plurality of bin histograms is associated with two corresponding threshold voltages, and wherein each bin histogram of the plurality of bin histograms reflects a count of memory cells of the memory that stores a voltage that is within the two corresponding threshold voltages associated with the corresponding bin histogram;
- identifying a first bin histogram of the plurality of bin histograms, wherein the plurality of bin histograms comprises (i) the first bin histogram and (ii) a plurality of neighboring bin histograms that neighbors the first bin histogram;
- and
- based on the plurality of neighboring bin histograms that neighbors the first bin histogram, determining a first log-likelihood ratio (LLR) for the first bin histogram,
- wherein the first LLR for the first bin histogram reflects a probability of the memory cells of the memory, which stores the voltage that is within the two corresponding threshold voltages associated with the first bin histogram, storing bit 0 or bit 1.
3 more elements
A memory system comprising:
- a memory comprising a plurality of memory cells;
- a read module configured to
- perform a plurality of read cycles on the plurality of memory cells of the memory,
- based on performing the plurality of read cycles on the plurality of memory cells of the memory, construct a plurality of bin histograms, wherein each bin histogram of the plurality of bin histograms is associated with two corresponding threshold voltages, and wherein each bin histogram of the plurality of bin histograms reflects a count of memory cells of the memory that stores a voltage that is within the two corresponding threshold voltages associated with the corresponding bin histogram,
- identify a first bin histogram of the plurality of bin histograms, wherein the plurality of bin histograms comprises (i) the first bin histogram and (ii) a plurality of neighboring bin histograms that neighbors the first bin histogram, and
- based on the plurality of neighboring bin histograms that neighbors the first bin histogram, determine a first log-likelihood ratio (LLR) for the first bin histogram, wherein the first LLR for the first bin histogram reflects a probability of the memory cells of the memory, which stores the voltage that is within the two corresponding threshold voltages associated with the first bin histogram, storing bit 0 or bit 1.
3 more elements
Dependencies are inferred from the claim text.