Reduced matrix Reed-Solomon encoding
AssigneeAltera Corporation
InventorsMartin Langhammer, Daniel Elphick
Life of this patent
Estimating the term…
Abstract
In an arrangement of the disclosed systems, devices, and methods, a matrix representation of a block code comprising m bit-planes is obtained, a generator matrix corresponding to each of the m bit-planes from the matrix representation is extracted, a transformed generator matrix and a transformed data symbol vector for the first bit-plane of the block code are determined, a reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code are determined, and instructions for the encoder architecture based on the transformed generator matrix for the first bit-plane and the reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code are generated.
Claims19
Circuitry for producing a plurality of check symbols comprising:
- input circuitry configured to receive a data vector comprising a plurality of data symbols, each data symbol having a bit-depth m;
- a plurality of adder banks comprising:
- a first adder bank configured to process the data vector to produce a transformed data vector by appending a plurality of parameters to the data vector;
- a plurality of m additional adder banks, each configured to process a respective bit-slice of the transformed data vector to produce an output based on a respective reverse-mapped generator matrix;
- and
- a reducer bank configured to process the outputs of each of the plurality of m additional adder banks to produce the plurality of check symbols.
A method for configuring an encoder architecture comprising:
- obtaining a matrix representation of a block code comprising m bit-planes;
- extracting a generator matrix corresponding to each of the m bit-planes from the matrix representation;
- determining a transformed generator matrix and a transformed data symbol vector for the first bit-plane of the block code;
- determining a reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code;
- and
- generating instructions for the encoder architecture based on the transformed generator matrix for the first bit-plane and the reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code.
Circuitry for producing a plurality of check symbols comprising:
- input circuitry configured to receive a data vector comprising a plurality of data symbols, each data symbol having a bit-depth m;
- for each of m bit-slices of a block code,
- a first adder bank configured to process the data vector to produce a transformed data vector based on the respective bit-slice;
- and
- a second adder bank configured to process the transformed data vector based on a reverse-mapped generator matrix for the bit-slice to produce an output;
- and
- a reducer bank configured to process the output of each second adder bank corresponding to each of the m bit-slices of the block code to produce the plurality of check symbols.
Dependencies are inferred from the claim text.