Methods, data storage devices and systems having variable size ECC page size

A method of controlling an array of flash memory devices responsive to data access commands from a host, comprising:

• receiving a host command to store host data in one or more of a plurality of blocks of the array of flash memory devices, each of the plurality of blocks comprising a plurality of flash pages (F-Pages), each of the plurality of F-Pages comprising an integer number of one or more error correcting code (ECC) pages (E-Pages), at least some of the E-Pages comprising a data portion and an ECC portion;
• selecting an ECC profile of a plurality of ECC profiles to apply to the one or more of the plurality of blocks, F-Pages or E-Pages to which the host data is to be stored;
• storing the host data in one or more logical pages (L-Pages);
• programming the one or more of L-Pages into the data portion of one or more of the plurality of E-Pages and generating an ECC code to be stored in the ECC portion of one or more of the plurality of E-Pages according to the selected ECC profile;
• and
• adjusting, in at least one of the F-Pages, a size of the ECC portion and correspondingly adjusting a size of the data portion of one or more E-Pages of the at least one F-Page according to a new ECC profile, wherein adjusting comprises decreasing the size of the data portion by an amount that the size of the ECC portion has been increased.

A solid state drive controller, comprising:

• a buffer configured to couple to an array of flash memory devices;
• and
• a processor coupled to the buffer, the processor being configured to program and read data from the array of flash memory devices responsive to data access commands from a host, the array of flash memory devices comprising a plurality of blocks, each comprising a plurality of flash pages (F-Pages), each of the plurality of F-Pages comprising an integer number of one or more error correcting code pages (E-Pages), at least some of the E-Pages comprising a data portion and an error correction code (ECC) portion,
• wherein the processor is further configured to:
• store a plurality of logical pages (L-Pages) in one or more of the plurality of E-Pages;
• and
• adjust, in at least one of the F-Pages, a size of the ECC portion and correspondingly adjust a size of the data portion of the E-Pages of the one or more E-Pages of the at least one F-Page,
• wherein the processor is further configured to decrease the size of the data portion by an amount that the size of the ECC portion has been increased.

A data storage device, comprising:

• an array of flash memory devices;
• and
• a controller coupled to the array of memory devices and configured to program and read data from the array of flash memory devices responsive to data access commands from a host, wherein the array of flash memory devices comprises:
• a plurality of blocks, each comprising a plurality of flash pages (F-Pages), each of the plurality of F-Pages comprising an integer number of one or more error correcting code pages (E-Pages), at least some of the E-Pages comprising a data portion and an error correction code (ECC) portion;
• wherein the controller is configured to:
• store a plurality of logical pages (L-Pages) in one or more of the plurality of E-Pages, at least some of the plurality of L-Pages being unaligned with boundaries of the E-Pages;
• and
• decrease a size of the data portion of one or more E-Pages of the at least one F-Page by an amount that a size of the ECC portion has been increased;
• and
• wherein, one of the plurality of blocks comprises:
• a first E-Page having an ECC portion of a first size;
• and
• a second E-Page having an ECC portion of a second size, wherein the second size is different from the first size, wherein the second size is selected based on a location of the second E-Page in the block.