Semiconductor storage device and control method of nonvolatile memory
AssigneeHitachi, Ltd.
InventorsTakashi Tsunehiro, Akifumi Suzuki, Junji Ogawa
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AssigneeHitachi, Ltd.
InventorsTakashi Tsunehiro, Akifumi Suzuki, Junji Ogawa
Estimating the term…
A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner.
A semiconductor storage device comprising:
A control method for a memory controller to control a read and a write of data to a nonvolatile memory that is provided with a plurality of pages, comprising the steps of:
Dependencies are inferred from the claim text.
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In individual solid state devices: in sector programmable memories, e.g. flash disk
Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals: online error correction
Computing and data processing
Static stores
About 6 years 4 months of term left · ends 23 Feb 2033 (estimated)
The present invention relates to a semiconductor storage device and a control method of a nonvolatile memory.
In recent years, a NAND type flash memory has been installed in a memory card, a solid state disk, or the like, and the demand of the flash memory has been increased from year to year. For the NAND type flash memory, the operations in data read and in data write are controlled by a memory controller. A memory controller that is provided with an error correction circuit (ECC circuit) adds the redundant information to data that has been input from a host apparatus and stores that data into the NAND type flash memory in a write of data (see Patent Literature 1 and Patent Literature 2). The memory controller reads data and the redundant information from the NAND type flash memory, detects an error point (an address for instance), and corrects an error of data in a read of data.
The data that is stored into a storage region of the NAND type flash memory is configured by a plurality of blocks. The data of each block is configured by a plurality of pages. For the NAND type flash memory, a write of data and a read of data are executed in a unit of a page. Moreover, for the NAND type flash memory, data is erased in a unit of a block.
FIG. 1 is an overall view showing an information processing system that is provided with a semiconductor storage device in accordance with an embodiment of the present invention.
FIG. 2 is an explanatory drawing showing a relationship between a block in an erasing unit and a page in a read/write unit for a NAND type flash memory.
FIG. 3 is an explanatory drawing showing a relationship between a page and a code word.
The embodiments for the present invention will be described below in detail with reference to the drawings. In the present embodiments, a NAND type flash memory will be described as an example of a nonvolatile memory. However, a nonvolatile memory is not restricted to a NAND type flash memory and a nonvolatile memory of other kind can also be used. For instance, the present invention can also be applied to a nonvolatile memory of other kind such as a resistance change type RAM (ReRAM), a phase change type RAM (PRAM®), and a magnetic resistance type RAM (MRAM).
The present embodiment utilizes a technical characteristic of a nonvolatile memory in which a bit error occurrence rate is different from each other for every page. In the present embodiment, a code word as an example of “data that is in a basic unit that is a unit of an error correction” is written to a plurality of pages in a dispersed manner. By this configuration, a bit error occurrence rate that is related to a code word becomes an average value of a bit error rate of a plurality of pages. As a result, it is not necessary that ECC (Error Check and Correct) circuits of a plurality of types are prepared, and the error correction ability can be implemented in an efficient way only by using an ECC circuit of one type.
A part of a page in which a bit error occurrence rate is high is used as one of a storage destination of a code word and a part of a page in which a bit error occurrence rate is low is used as other one of a storage destination of a code word for instance. In this case, a bit error occurrence rate for the entire code words is an average value of a high bit error occurrence rate and a low bit error occurrence rate. Consequently, in the case in which an ECC circuit that is corresponded to the average bit error occurrence rate, the error correction ability can be obtained without excess and deficiency.