Apparatus and method for detecting an error within a coded binary word

An apparatus for detecting a faulty behavior of an error corrector due to a transient or permanent hardware error, comprising:

• the error corrector configured to correct a correctable bit error within at least a faulty subset of bits of a faulty coded binary word coded by an error correction code and to output the coded binary word in which the correctable bit error is corrected;
• and
• an error detector configured to receive an error detector input binary word based on at least an output of the error corrector, and determine an error detection bit sequence indicating whether or not the error detector input binary word is a code word of the error correction code;
• wherein the apparatus is configured to detect the faulty behavior of the error corrector in case the error detection bit sequence indicates that the error detector input binary word is not a code word of the error correction code even though a code word of the error correction code or a faulty word which is correctable by the error correction code is input into the error corrector, and
• wherein the error detector is configured to determine the error detection bit sequence based on a multiplication of an error detection matrix and the error detector input binary word, wherein the error detection matrix is based on a check matrix of the error correction code.

An apparatus for detecting a faulty behavior of an error corrector due to a transient or permanent hardware error, comprising:

• the error corrector configured to correct a correctable bit error within at least a faulty subset of bits of a faulty coded binary word coded by an error correction code and to output the coded binary word in which the correctable bit error is corrected;
• and
• an error detector configured to receive an error detector input binary word based on at least an output of the error corrector, and determine an error detection bit sequence indicating whether or not the error detector input binary word is a code word of the error correction code;
• wherein the apparatus is configured to detect the faulty behavior of the error corrector in case the error detection bit sequence indicates that the error detector input binary word is not a code word of the error correction code even though a code word of the error correction code or a faulty word which is correctable by the error correction code is input into the error corrector, and
• wherein the coded binary word comprises data bits, check bits of the error correction code and address bits, wherein the error corrector is configured to correct a correctable bit error within the data bits and the check bits only, wherein the corrected coded binary word is based on the output of the error corrector and the address bits of the coded binary word.

An apparatus for detecting a faulty behavior of an error corrector due to a transient or permanent hardware error, comprising:

• the error corrector configured to correct a correctable bit error within at least a faulty subset of bits of a faulty coded binary word coded by an error correction code and to output the coded binary word in which the correctable bit error is corrected;
• an error detector configured to receive an error detector input binary word based on at least an output of the error corrector, and determine an error detection bit sequence indicating whether or not the error detector input binary word is a code word of the error correction code;
• wherein the apparatus is configured to detect the faulty behavior of the error corrector in case the error detection bit sequence indicates that the error detector input binary word is not a code word of the error correction code even though a code word of the error correction code or a faulty word which is correctable by the error correction code is input into the error corrector;
• and
• a combiner configured to determine the error detector input binary word by combining a coded binary word which is based the output of the error corrector and a second coded binary word, so that the error detector input binary word is a code word of the same error correction code if the corrected coded binary word and the second coded binary word are code words of the error correction code, and so that the error detector input binary word is not a code word of the error correction code if the corrected coded binary word or the second coded binary word is not a code word of the error correction code.

A circuitry S for detecting errors in a circuit for correcting errors in code words of a linear error correction code C, comprising:

• an error correction circuit, wherein the error correction circuit comprises n binary inputs for the input of an n-component binary word v′=v′1 . . . , v′n, comprising two bit groups v′1=v′1, . . . , v′p and v′2=v′p+1, . . . , v′n and p outputs for outputting p corrected bits of the first bit group vcorr1=vcorr,1, . . . , vcorr,p, wherein 1≦p≦n applies,
• wherein the linear error correction code comprises code words v=v1, . . . , vn=v1, v2 of the length n with q, q<n information bits, wherein the code words comprise a first group of bits v1=v1, . . . , vp and a second group of bits v2=vp+I, . . . , vn, wherein errors in the first group of bits are corrected by the error correction circuit in vcorr1 and errors in the second bit group of bits are not corrected, and wherein the bits vcorr1 of the first bit group corrected by the error correction circuit and the non-corrected bits v′2 of the second bit group form the n-digit binary word vcorr=vcorr1,v′2, wherein vcorr1 is output by the error correction circuit,
• wherein the error correction circuit is set up so that when inputting a code word vεC, vcorr=v applies, when the error correction circuit is not erroneous;
• and
• an error detection circuit with n binary inputs and I binary outputs A1, . . . , AI, and configured to output an I-component error signal f1 . . . , fI exists, which forms the error signal f=f1 . . . , fI for I determined binary values i1, i2 . . . iI so that for an input of any code word vcorr of the code C for the components of the error signal
• f1i1=f2i2= . . . =flil
• applies, and configured to input a non-code word vcorr, not all components f1i1, f2i2, . . . , fIiI of the components of the error signal are equal and the error detection circuit indicates an error when not all values of the components f1i1, f2i2, . . . , fIiI of the error signal f are equal and I≦n−q applies, and wherein fjij= fj for j=1, . . . , I applies, if ij=0 applies, and fjij=fj, ij=1 applies,
• wherein the n binary inputs of the error detection circuit are arranged to receive an input based on the n-digit binary word vcorr=vcorr1,v′2, wherein vcorr1 is output by the error correction circuit.

A method for detecting a faulty behavior of an error corrector due to a transient or permanent hardware, the method comprising:

• inputting a code word of an error corrections code or a faulty word which is correctable by the error correction code into an error corrector configured to correct a correctable bit error within at least a subset of bits of a coded binary word coded by the error correction code and to output the coded binary word in which the correctable bit error is corrected;
• determining using an error detector an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code, wherein the error detector input binary word is based on at least an output of the error corrector received at the error detector;
• and
• detecting the faulty behavior of the error corrector in case the error detection bit sequence indicated that the error detector input binary word is not a code word of the error correction code even though the code word of the error correction code or the faulty word which is correctable by the error correction code was input to the error corrector,
• wherein the error detection bit sequence is determined using the error detector so that the error detection bit sequence is equal to a first predefined detection bit sequence for a first subset of code words of the error correction code and equal to a second predefined detection bit sequence for a second subset of code words of the error correction code, wherein the first predefined detection bit sequence is different from the second predefined detection bit sequence and the first subset of code words of the error correction code is different from the second subset of code words of the error correction code.