DDR JTAG interface setting flip-flops in high state at power-up

#This disclosure relates to a JTAG interface that uses double data rate circuitry for accessing devices on a substrate using a reduced number of device pins.

#Electrical devices, which may be boards, ICs or embedded cores within ICs, use JTAG interfaces to provide for testing and debugging of the device's hardware and software designs. In the past, device test and debug interfaces used the full pin JTAG interface consisting of a TDI, TCK, TMS, TDO, and an optional TRST pin. More recently, reduced pin JTAG interfaces are being developed and used for test and debug when device pins are not available for the full pin JTAG interface. Some known reduced pin JTAG interfaces include; (1) a simultaneously bidirectional transceiver (SBT) based reduced pin JTAG interface described in a 2006 International Test Conference paper by Whetsel which is incorporated by reference herein, (2) an IEEE standard P1149.7 described in a white paper which is incorporated by reference herein, (3) a JTAG Link (JLINK) interface developed by DebugInnovations which is incorporated by reference herein, and (4) a single wire JTAG (SWJ) interface developed by ARM Ltd which is incorporated by reference herein. Reducing the number of JTAG pins, while enabling access to pin limited device, brings about a reduction in the communication bandwidth between a JTAG controller and JTAG device. The disclosure describes a JTAG interface based on double data rate circuitry that reduces JTAG pins while advantageously maintaining a high communication bandwidth between a JTAG controller and JTAG device. The double data rate JTAG interface may be used for device test, debug, programming or other operations performed today by the JTAG bus.

#FIG. 1 illustrates an example of a full pin JTAG interface bus 102 coupled between a JTAG TAP controller 104 and JTAG TAP domain 106 within a device 108. The TAP domain is an IEEE 1149.1 based architecture that includes a TAP state machine, an instruction register, and plural data registers. The TAP domain 106 may be used for testing, debugging, or programming of the device 108. The full pin JTAG (IEEE 1149.1) interface 102 comprises a TDI, TCK, TMS, TDO and optionally a TRST signal. Pull up (PU) elements 105 are required on the TDI and TMS inputs of the device 108 to pull these signals high if they are not externally driven by the controller 104. Pulling TMS high causes the TAP state machine of the TAP domain 106 to remain in the Test Logic Reset state of FIG. 12A. If the optional TRST signal is not used, a power up reset (POR) circuit 110 may be used in the device 108 to reset the TAP domain when the device powers up. The device's TAP domain 106 can also be reset by an input sequence from the TAP controller 104 on bus 102.

#FIG. 1 illustrates an interface between a JTAG TAP controller and a TAP domain within a device.

#FIG. 2 illustrates a double data rate (DDR) circuit for communicating data between a sending and receiving circuit.

#FIG. 3 illustrates a DDR circuit for communicating TDI and TMS signals from a TAP controller to a TAP domain according to the disclosure.

#FIG. 3 illustrates the DDR circuit 202 of FIG. 2 being used to provide a high speed, reduced pin JTAG interface between a TAP controller 302 and a TAP domain 106 within a device, according to the disclosure. The reduced pin interface is achieved by combining the separate TDI and TMS signals of the TAP controller 104 of FIG. 1 into serialized signal components that are output from the TAP controller 302 to DDR circuit 202 via the single TDI/TMS signal from TAP controller 302. As seen in the timing diagram, the operation of the DDR circuit is the same as described in FIG. 2. The only differences are that the A component of the A/B signal from the sending circuit 204 is now the TDI component of the TDI/TMS signal from the TAP controller 302, the B component of the A/B signal from the sending circuit 204 is now the TMS component of the TDI/TMS signal from the TAP controller 302, and the clock signal from sending circuit 204 is now the TCK signal from the TAP controller 302. Rising TCK edges 224 clock in the TDI component of TDI/TMS to DDR circuit 202 and falling TCK edges 226 clock in the TMS component of TDI/TMS to DDR circuit 202.

#FIG. 3A illustrates an example implementation of the TAP controller 302 of FIG. 3, which comprises the TAP controller 104 of FIG. 1 and an adapter circuit 308. The adapter circuit 308 serves to convert the separate TDI and TMS signal outputs from TAP controller 104 into the single TDI/TMS signal output of FIG. 3. The single TDI/TMS signal output serially transmits the TDI and TMS signal components to the DDR circuit 202 of FIG. 3.

#FIG. 3B illustrates an example implementation of the adapter circuit 308, which comprises a multiplexer 310, a TCK clock doubler 312, a state machine 314, and flip flops 316 and 318 connected as shown. The clock doubler 312 inputs the TCK and outputs a doubled TCK signal (2×TCK) to the state machine 314. The state machine inputs the 2×TCK signal and outputs a select signal to multiplexer 310 and flip flops 316 and 318. The rising edge of the select signal latches the TDI and TMS signals from TAP controller 104 to multiplexer 310, via flip flops 316 and 318, to keep them stable during the serialization process. The select signal controls the multiplexer 310 to alternately output the latched TDI and TMS signals onto the TDI/TMS signal to DDR circuit 202. The clock doubler 312 and state machine 314 are initialized in response to a low on the TRST signal output from TAP controller 104.