At-speed scan testing of clock divider logic in a clock module of an integrated circuit

A method comprising:

• providing clock signals to respective portions of an integrated circuit from at least one clock module comprising one or more clock dividers and associated clock divider logic;
• and
• configuring scan test circuitry of the integrated circuit to permit testing of at least a portion of the associated clock divider logic of the at least one clock module;
• wherein the scan test circuitry is coupled to a clock distribution network comprising the at least one clock module.

A processing system comprising:

• a processor;
• and
• a memory coupled to the processor and configured to store information characterizing an integrated circuit design;
• wherein the processing system is configured to provide scan test circuitry and a clock distribution network within the integrated circuit design, the scan test circuitry comprising at least one scan chain having a plurality of scan cells, the clock distribution network being configured to provide a plurality of clock signals to respective portions of the scan test circuitry;
• the clock distribution network comprising:
• at least one clock module comprising one or more clock dividers and associated clock divider logic;
• wherein the scan test circuitry is coupled to the clock distribution network and configured to permit testing of at least a portion of the associated clock divider logic of the at least one clock module.