Fault-tolerant computer system

A system for providing a fault-tolerant basis to execute instructions, the system comprising:

• one or more processors;
• an error detector executable by the one or more processors to detect a first error in the execution of an instruction in a faulty stage unit of a first pipeline unit in a first core, the error detector further configured to determine if a second error occurs in the execution of a rewritten instruction in the first pipeline unit and to determine whether a third error occurs in the execution of the instruction in the first substitute stage unit of the second pipeline unit and the non-faulty stage units of the first pipeline unit;
• a rewriting engine communicatively coupled to the error detector, the rewriting module executable by the one or more processors to rewrite the instruction to form the rewritten instruction in response to the detection of the first error;
• a recovery engine communicatively coupled to the error detector and the rewriting module, the recovery engine executable by the one or more processors to execute the rewritten instruction in the first pipeline unit, the recovery engine further configured to:
• select a first substitute stage unit for the faulty stage unit from a second pipeline unit in the first core responsive to determining the occurrence of the second error,
• re-execute the instruction in the first substitute stage unit of the second pipeline unit and non-faulty stage units of the first pipeline unit in the first core;
• and
• re-execute the instruction in a second substitute stage unit of a third pipeline unit in a second core responsive to detecting the third error;
• a fault locator communicatively coupled to the error detector and the recovery engine, the fault locator executable by the one or more processors to locate a faulty component for the faulty stage unit;
• and
• a fallback programming module communicatively coupled to the recovery engine and the fault locator, the fallback programming module executable by the one or more processors to establish a fallback unit for the faulty component.

A computer program product comprising a non-transitory computer readable medium storing a computer readable program that, in response to execution by a computing device, causes the computing device to perform operations comprising:

• detecting a first error in the execution of an instruction in a faulty stage unit of a first pipeline unit in a first core;
• rewriting the instruction to form a rewritten instruction in response to the detection of the first error;
• executing the rewritten instruction in the first pipeline unit;
• determining if a second error occurs in the execution of the rewritten instruction;
• responsive to determining the occurrence of the second error,
• selecting a first substitute stage unit for the faulty stage unit from a second pipeline unit in the first core, and
• re-executing the instruction in the first substitute stage unit of the second pipeline unit and non-faulty stage units of the first pipeline unit in the first core;
• determining whether a third error occurs in the execution of the instruction in the first substitute stage unit of the second pipeline unit and the non-faulty stage units of the first pipeline unit;
• responsive to detecting the third error, re-executing the instruction in a second substitute stage unit of a third pipeline unit in a second core;
• locating a faulty component for the faulty stage unit;
• and
• establishing a fallback unit for the faulty component.