US 8,898,504 B2Granted

Parallel data communications mechanism having reduced power continuously calibrated lines

AssigneeInternational Business Machines Corporation

InventorsSteven J. Baumgartner, Frank D. Ferraiolo, Susan M. Eickhoff, Michael B. Spear

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Abstract

A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed NMAX. When N<NMAX, lines not carrying functional data are partially powered down between calibrations.

Claims20

Dependent claims

A communications mechanism for communicating between digital data devices, comprising:

a first plurality of parallel lines supporting a parallel communications link for communicating data in a first direction from a first digital data device to a second digital data device;
a calibration mechanism for periodically recalibrating each line of said first plurality of parallel lines;
a switching mechanism coupled to said first plurality of parallel lines for selectively enabling each line of said first plurality of parallel lines to carry functional data;
said communications mechanism supporting at least a first mode of operation wherein, with respect to each line of a first subset of said first plurality of parallel lines, at least some respective circuitry required for transmission of functional data in the respective line is powered down during respective time intervals between calibration of the respective line, said first subset containing at least one line of said first plurality of parallel lines and fewer than all of said first plurality of parallel lines, wherein corresponding respective circuitry required for transmission of functional data in each line of said first plurality of parallel lines not in said first subset is not powered down.

1 more element

A digital data processing apparatus, comprising:

a plurality of digital data modules;
at least one parallel communications link for communicating data between a first module of said plurality of digital data modules and a second module of said plurality of digital data modules, said at least one parallel communications link having a plurality of parallel lines supporting data communication in a first direction from said first module to said second module, said plurality of parallel lines being continuously calibrated;
a bus width control mechanism for selectively operating said parallel communications link in a plurality of modes corresponding to different bus widths, including a first mode in which exactly N1 lines of said plurality of parallel lines are used for communicating functional data from said first module to said second module and a second mode in which exactly N2 lines of said plurality of parallel lines are used for communicating functional data from said first module to said second module, wherein N2<N1, wherein in said second mode of operation, at least (N2−N1) lines of said plurality of parallel lines are at least partially powered down while remaining continuously calibrated.

Dependencies are inferred from the claim text.